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- In a digital communication, explain all the methods/mechanism used for the minimization of Bit Error Rate (BER). Also state that which method/mechanism is preferred and why?Microprocessors; Draw the figure for flag-bits allocation in an 8086 microprocessor. Explain shortly the meanings of letters used for each flag statues in Assembler.Q1. Refer to the truth table in Table Q(a) Find the Boolean expression for function Z(b) Using not more than 10 transistors, draw the gate-level and transistor-level schematics for the Boolean function.
- 4. What will be the minimum number of 2-input NAND gates required implement the following expression? (EXPRESSION IN PICTURE ATTACHED)S Display will be designed for a thermometer. The display will show that degree for minimum temperature and 99 degrees for maximum temperature. According to this; a) What is the number of bits that will be needed in the binary code to express the temperature? b) What are the binary, octal and hexadecimal equivalents of 95 degrees? () What is the BCD representation of 95 degrees? d) What is the hex equivalent of this temperature when it shows 111 degrees octal? e) If the thermometer showed a temperature between -99 and +99 degrees, how many bits would we need?Draw the logic diagram for the simplified expression using NAND Gates
- Design a 3-bit synchronous binary counter using JK flip-flop. State Table: 3-bit synchronous binary counter:A certain packaged IC chip can dissipate 5W. Supposewe have a CMOSIC design that must fit on onechip and requires 10 million logic gates. What is theaverage power that can be dissipated by each logicgate on the chip? If the average gate must switch at100 MHz, what is the maximum capacitive load ona gate for VDD =3.3 V, 2.5 V and 1.8 V.1) Draw how an ASIC, SOC, MCU, MPU, DSP any TTL gates of the TTL circuits you have constructed or designed to use a transistor (BJT/MOS) to drive the current specification of a LOAD (ie RELAY, Motor, Light array of High powered LEDs)