A certain packaged IC chip can dissipate 5W. Supposewe have a CMOSIC design that must fit on onechip and requires 10 million logic gates. What is theaverage power that can be dissipated by each logicgate on the chip? If the average gate must switch at100 MHz, what is the maximum capacitive load ona gate for VDD =3.3 V, 2.5 V and 1.8 V.
A certain packaged IC chip can dissipate 5W. Supposewe have a CMOSIC design that must fit on onechip and requires 10 million logic gates. What is theaverage power that can be dissipated by each logicgate on the chip? If the average gate must switch at100 MHz, what is the maximum capacitive load ona gate for VDD =3.3 V, 2.5 V and 1.8 V.
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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A certain packaged IC chip can dissipate 5W. Suppose
we have a CMOSIC design that must fit on one
chip and requires 10 million logic gates. What is the
average power that can be dissipated by each logic
gate on the chip? If the average gate must switch at
100 MHz, what is the maximum capacitive load on
a gate for VDD =3.3 V, 2.5 V and 1.8 V.
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