6. Fill in the table below, assuming each instruction can impact the subsequent instructions. instruction destination result value source value addl %ecx.(%eax) sarl 2, %ebx leal 4(%eax,%edx,4),%esi movl %eax, %ebx movl (%eax), %edi
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- 6. Fill in the requested register values on the right side of the following instruction sequence:mov esi,OFFSET myBytesmov ax,[esi] ; a. AX =mov eax,DWORD PTR myWords ; b. EAX =mov esi,myPointermov ax,[esi+2] ; c. AX =mov ax,[esi+6] ; d. AX =mov ax,[esi-4] ; e. AX =Please write down the microinstructions to implement the instruction MOV R0, [R1], moving the contents of the memory cell pointed by R1 tothe register R0. Please add a short but significant explanation to each single microinstruction. olve this question in great detail explaining every single bit of info as i'm a complete beginner and i need to understand how to solve questions of this type. also provide small examples of how the solution would differ if the question was slightly altered. THANK YOU!In this case, every instruction receives its own data, independent of how the data for other instructions is obtained. We make advantage of a: A Multiple Data/Instruction B Multiple Iterations of Data or Instruction C Singular Data Single Inst D Singe Inst Multiple
- Rearrange the following code to minimize the total number of cycles, assuming that a dependent instruction following the load will need two clock cycles of delay before getting the data. Load r1, 64 (r2)Add r2, r2, r2Sub r3, r4, r1Load r4, 32 (r4)Add control states to the following to implement an exchange-with-memory instruction, xchg. such that xchg $rt,immed($rs) acts rather like the combination of a MIPS lw and sw: the result should be as if a sequence like t=memory[immed+rs]; memory[immed+rs]=rt; rt=t; where t is a temporary register. In case you were wondering why one would ever want to do this, it's actually a very common operation for synchronizing between concurrently executing processes using sempahores... but MIPS doesn't happen to do it this way, so it's also not a MIPS instruction. You're probably wondering where the t register is. Well, pick one you're not using... perhaps y (although you have to be careful about when you compute immed+rs for that to work). You should use the encoding suggested by the when below, so an instruction like xchg $9,4($10) would be encoded as op(3)+rt(9)+rs(10)+immed(4). when (op()) (op(3)) XchgStart: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin,…Please answer this question and provide the explanation Assume the values of %ecx is 0x00000005 and %edx is 0x00000003. What would be the value of %ecx and %edx after performing the following instruction? 0x5555555461a <+0>: leal (%ecx, %edx, 8), %edx %ecx = 0x00000005, %edx = 0x0000003A %ecx = 0x00000005, %edx = 0x00000018 %ecx = 0x00000005, %edx = 0x00000030 %ecx = 0x00000005, %edx = 0x00000003 %ecx = 0x00000005, %edx = 0x0000001D %ecx = 0x00000005, %edx = 0x00000040 %ecx = 0x00000055, %edx = 0x0000001D %ecx = 0x00000005, %edx = 0x0000002A %ecx = 0x00000005, %edx = 0x00000025 %ecx = 0x00000005, %edx = 0x00000035
- Read the Assembly program carefully, understand its working/functionality and answer the below given question. MOV DX, 0090 MOV DS, DX MOV BX, 0010 MOV SI, 0020 MOV AL,00 MOV DL, [SI] MOV CX, 000AP1: CMP DL, [BX] JNZ P2 ;JNZ is Jump if ZF=0 in the result of CMP instruction INC ALP2: INC BX INC SI DEC CX MOV DL, [SI] CMP CX, 0 JA P1 MOV [0030], AL INT E0090:0010 DB B8, 6F, 23, D0, 99, C5, 89, 9D, 1A, 810090:0020 DB 37, 6F, 32, B6, 11, C5, 98, 2B, 7A, C0 a. What will be displayed on the LCD after the execution of program?I- Explain utiat haprns PUSH Bx instruction executes. Make sure to show where BH and BL are stored (assume that SP=OI OOh and SS=0200h) 2- Show the ending auress of each memory segments for the follow.ng segment register values: SS=ABCDw CS=EOOOh, DS=FOFOW cs=1234h 3- Sumx»se ECx-12345678h , EBx—876S4321h DS-1100tL Determine the contents of each address accessed by the following instructions: (a) MOV [EBx].ECx (b) MOV WORD PTRIEBx J, 1234bIf R0 = 0x8000 and memory data layout is as below, what are the r1 and r0 register values, respectively, after LDR r1, [r0], #4 instruction (data layout big endian)? A. r1= 0x1A2CEB0D, r0 = 0x8000 B. r1=0x0dEB2C1A, r0 = 0x8000 C. r1=0x79CDA3FD, r0 = 0x8000 D. r1= 0x1A2CEB0D, r0 = 0x8004 E. r1= 0x79CDA3FD, r0 = 0x8004
- In the following code sequence, show the value of AL after each shift or rotate instructionhas executed:mov al,0D4hshr al,1 ; a.mov al,0D4hsar al,1 ; b.mov al,0D4hsar al,4 ; c.mov al,0D4hrol al,1 ; dA subtraction instruction takes two operands, subtracts the first from the second, and the result goes into the second. Write a 16-bit subtraction instruction, where... The first operand is stored at the memory address contained within the %edx register. (NOTE: To be clear, the %edx register contains the memory address OF the operand, not the operand itself! Recall the syntax of "indirect addressing," to use here.) The second operand -- also where the result shall be stored -- is stored directly in the 16-bit %bp register. Type the appropriate assembly language instruction here:Consider the following program in MARIE assembly language. a) Complete the table detailing the RTN for next 2 instructions only that will be executed including the content of registers PC, IR, MAR, MBR and AC in hexadecimal. Note the first instruction LOAD X is already filled. Note also that SKIPCOND instruction has no operands, therefore you can complete Fetch, decode and execute cycles only. b) Explain in one statement the task performed by this program?