b. i. Using a detailed state diagram, explain how the instruction cycle can be expanded including the interrupt sub cycle and indirect sub cycle. ii. Following description is about values stored at particular memory locations and registers when a set of instructions are executed by the processor. An instruction is stored at memory addresses 100. Assume that the address field of the instruction has the value 300. Content of memory address,300 is 410. Further, assume that the 'content of memory address 400 is 340. The program counter has the value 100 for fetching this instruction. The content of processor register R is 730, and the content of index register XR is 201. o According to the given information, determine the operand values when the direct and indirect addressing modes are used. o Evaluate the effective address for each of the following addressing modes. o Register Indirect o Relative o Indexed

b. i. Using a detailed state diagram, explain how the instruction cycle can be expanded including the interrupt sub cycle and indirect sub cycle. ii. Following description is about values stored at particular memory locations and registers when a set of instructions are executed by the processor. An instruction is stored at memory addresses 100. Assume that the address field of the instruction has the value 300. Content of memory address,300 is 410. Further, assume that the 'content of memory address 400 is 340. The program counter has the value 100 for fetching this instruction. The content of processor register R is 730, and the content of index register XR is 201. o According to the given information, determine the operand values when the direct and indirect addressing modes are used. o Evaluate the effective address for each of the following addressing modes. o Register Indirect o Relative o Indexed

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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1, Explain how we can find the address location of INT 0AH in Interrupt vector table. 2. What will be the content of AX register after execution of the instruction IMULCL, if CL = +1510 and AL = -13210.. 3. Suppose that DS = 1300H, SS = 1280H, BP = 15A0H and SI = 01D0H.Determine the address accessed by each of the following instructions andmention their type of addressing mode.i) MOV AX, [200H]ii) MOV AL, [BP-SI+200H]iii) ADD AL, [SI + 0100H]
6. Suppose that the interrupt processing method of is to store the breakpoint in the address of 00000Q unit, and fetch the instruction from the 77777Q unit (that is the first instruction of the interrupt service routine) and execute it. Write the micro-operations sequence that completes this function.
19. The 8085 microprocessor respond to the presence of an interrupt a. As soon as the trap pin becomes ‘LOW’ b. By checking the trap pin for ‘high’ status at the end of each instruction fetch c. By checking the trap pin for ‘high’ status at the end of execution of each instruction d. By checking the trap pin for ‘high’ status at regular intervals
17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…
Problem: Consider a processor with FOUR general purpose registers only. i. Write control sequence for adding the content of the memory location whose address is at memory location pointed by immediate number NUM to register R1. Assume the number NUM is provided by control unit. ii. List factors which contribute to generate control signals with at least on example of each factor
In this exercise, we examine in detail how much an instruction is executed in a single-cycle Datapath. The problem refers to a clock cycle in which the processor fetches the following instruction word: 1010 1100 0110 0010 0000 0000 0001 0100. Assume that data memory is all zeros and that the processor's registers have the following values at the beginning of the cycle in which of the instruction word is fetched: (See image attached) What is the new PC address after this instruction is executed? Highlight the path through which this value is determined?
The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Ø Immediate Mode Ø Direct Mode Ø Register Ø Relative Mode Ø Index Mode Choose your own values for variables (v – w), T1, T2. Choose any one of the given value for T3 (200 or 300). V=700 W=800 T1=200 T2=200 T3=300
The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction.The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Immediate Mode  Direct Mode Register Relative Mode Index ModeNote: Choose your own values for variables k – w, T1, T2. Choose any one of the given value for T3 (200 or 300).
Problem: Consider a processor with FOUR general purpose registers only. i. Draw block diagram of the processor with two internal buses. ii. List ALL operations ALU is able to perform iii. Write all control signals to perform all operations including those listed in part (ii) iv. Write control sequence for adding the content of the memory location whose address is at memory location pointed by immediate number NUM to register R1. Assume the number NUM is provided by control unit. v. List factors which contribute to generate control signals with at least on example of each factor
Assume that the state of the 8088’s registers and memory just prior to the executionof each instruction in problem 15 is as follows: * in photos*What result is produced in the destination operand by executing instructions (a)through (k)? *only h through k* (h) MUL DX(i) IMUL BYTE PTR [BX+SI](j) DIV BYTE PTR [SI]+0030H(k) IDIV BYTE PTR [BX][SI]+0030H
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Consider the following store instruction: SW R1, 0x000F(R0). Assume that the registers R0 and R1 are initialized with 0x00000001 and 0x53A78BC Frespectively. A section of the MIPS byte addressable data memory is shown. Give the memory word of the following memory locations after the SW operation: (a). 0x00000015. (b). 0x00000014. (c). 0x00000013. (d) 0x00000012.(e). 0x00000011. (f). 0x00000010.