Problem: Assume that all memory access operations are completed in one clock cycle in a processor that has a 1-GHz clock. What is the frequency of memory access operations if Load and Store instructions constitute 20 percent of the dynamic instruction count in a program? (The dynamic count is the number of instruction executions, including the effect of program loops, which may cause some instructions to be executed more than once.) Assume that all instructions are executed in 5 clock cycles.

Problem: Assume that all memory access operations are completed in one clock cycle in a processor that has a 1-GHz clock. What is the frequency of memory access operations if Load and Store instructions constitute 20 percent of the dynamic instruction count in a program? (The dynamic count is the number of instruction executions, including the effect of program loops, which may cause some instructions to be executed more than once.) Assume that all instructions are executed in 5 clock cycles.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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1. In this exercise we examine in detail how an instruction is executed in a single cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: 10001100101001100000000000111000 Assume that the data memory is all zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched: R0 R1 R2 R3 R4 R5 R6 R8 R12 R3 1 0 1 -2 4 -6 4 -10 -12 -14 31 a. What are the outputs of the sign-extend and the jump “Shift-Left-2” (near the top of the following Figure) for this instruction word? b. What are the values of ALU control unit’s inputs (ALUOp and Instruction operation) for this instruction? c. For the ALU and the two add units, what are their data input values? ALU Add (PC+4) Add (Branch) Input#1 Input#2 Input#1 Input#2 Input#1 Input#2
Assume for arithmetic, load/store, and branch instructions, a processor has CPIs for 1, 12, and 5respectively. Also assume that on a single processor a program requires the execution of 2.56*10^9arithmetic instructions, 1.28*10^9 load/store instructions, and 256 million branch instructions. Assumethat each processor has a 2GHz clock frequency. Assume that, as the program is parallelized to run overmultiple cores, the number of arithmetic and load/store instruction per processor is divided by 0.7xp(where p is the number of processors) but the number of branch instructions per processor remains thesame. a- Find the total execution time for the program on 1,2,4, and 8 processors, and show the relativespeedup of the 2,4, and 8 processor result relative to single processor result. b- If the CPI of the arithmetic instruction was doubled, what would be the impact be on theexecution time of the program on 1,2,4, and 8 processors? c- To what should the CPI of load/store instructions be…
Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following a )What is the total cycle in single-cycle implementation? b )What is the total cycle in pipelining implementation? c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?
Assume that a program requires the execution of 125x106 FP (floating point) instructions, 130x106 INT (integer) instructions, 150x106 L/S (load/store) instructions, and 110x106 branching instructions. These instructions have CPIs of 1, 1, 8 and 4, respectively. Assume that the processor has a 5 GHz clock rate. a. Is it possible to run the program twice as fast if we improve the CPI of just the L/S instructions? If so, by how much? Show your calculations. b. What is the Speedup in the execution time of the entire program if the CPI of INT and FP instructions is reduced by 40% and that of L/S and branching instructions is reduced by 50%?
The importance of having a good branch predictor depends on how often conditional branches are executed. Together with branch predictor accuracy, this will determine how much time is spent stalling due to mispredicted branches. In this exercise, assume that the breakdown of dynamic instructions into various instruction categories is as follows: R-Type BEQ JMP LW SW 40% 25% 5% 25% 5% Also, assume the following branch predictor accuracies: Always - Taken Always - not - taken 2-bit 40% 60% 75% 1.1 Stall cycles due to mispredicted branches increase the CPI. What is the extra CPI due to mispredicted branches with the always-taken predictor? Assume that branch outcomes are determined in the EX stage, that there are no data hazards, and that no delay slots are used. 1.2 Repeat 1.1 for the “always-not-taken” predictor. 1.3 Repeat 1.1 for the 2-bit predictor. 1.4 With the 2-bit predictor, what speedup would be achieved if we could convert half of the branch instructions in a way…
- Compilers can have a profound impact on the performance of an application.Assume that for a program, compiler A results in a dynamic instruction count of1.0 × 109 and has an execution time of 1.15 s, while compiler B results in adynamic instruction count of 1.2 × 109 and an execution time of 1.56 s.a) Find the average CPI for each program given that the processor has aclock cycle time of 1 ns.b) Assume the compiled programs run on two different processors. Ifthe execution times on the two processors are the same, how muchfaster is the clock of the processor running compiler As code versusthe clock of the processor running compiler B’s code?
(15pt) Assume that instruction cache miss rate is 2%, data cache miss rate is 10%, CPI (clock cycle per instruction) is 2 without any memory stall, and miss penalty is 100 cycles. In addition, assume that the frequency of loads/stores is 30%. (a) Compute CPI with memory stall. (b) When CPI without any memory stall becomes 1, compute CPI with memory stall. (c) If the CPU clock rate is doubled with the same memory when CPI without memory stall is 2, compute CPI with memory stall.
Consider a HW ISA program P1 with the following Instruction Memory IM: a. fill in the execution table for program P1 using the IM. Use the same notational conventions used in the example execution table for P0 below. Any numbers beginning with 0x will be interpreted as hexidecimal; any numbers not beginning with 0x will be interpreted as decimal. b. Show the final values of the registers R2, R3, and R4 when the program execution halts. Again, any numbers beginning with 0x will be interpreted as hexidecimal; any numbers not beginning with 0x will be interpreted as decimal.
1. We wish to compare the performance of two different machines: M1 and M2. The following measurements have been made on these machines: Program Time on M1 Time on M2 1 10 seconds 5 seconds 2 3 seconds 4 seconds Which machine is faster for each program, and by how much? 2. For M1 and M2 of problem 1, the following additional measurements are made:. Find the instruction execution rate (instructions per second) for each machine when running program 1. Program Instructions executed on M1 Instructions executed on M2 1 200 x 106 160 x 106 3. For M1 and M2 of problem 1, if the clock rates are 200 MHz and 300 MHz, respectively, find the CPI for program 1 on both machines using the data provided in problems 1 and 2. 4. You are going to enhance a machine, and there are two possible improvements: either make multiply instructions run four times faster than before or make memory access instructions run two times faster than before. You…
The importance of having a good branch predictor depends on how often conditional branches are executed. Together with branch predictor accuracy, this will determine how much time is spent stalling due to mispredicted branches. In this exercise, assume that the breakdown of dynamic instructions into various instruction categories is as follows: Also, assume the following branch predictor accuracies: Stall cycles due to mispredicted branches increase the CPI. What is the extra CPI due to mispredicted branches with the always-taken predictor? Assume that branch outcomes are determined in the EX stage, that there are no data hazards, and that no delay slots are used. b. With the 2-bit predictor, what speedup would be achieved if we could convert half of the branch instructions in a way that replaces a branch instruction with an ALU instruction? Assume that correctly and incorrectly predicted instructions have the same chance of being replaced.
In a register/memory type CPU, the instruction lengths are typically variable. This presents a problem when the program is incremented during the Fetch-Decode-Execute cycle. What statements(s) is/are NOT TRUE with regard to Program Counter (PC) incrementing? Select one or more A. The binary loader overcomes the problem by positioning instructions at word boundaries so that PC can be calculated. B . PC is incremented by the largest possible foxed value, irrespective of the variability of the instruction C. Increment value is known when the current instruction has completed execution. D. increment value is known when the current instruction is decoded with the Instruction Register (IR) E. PC incrementing method is implementation dependent
4.19.16: [5] <COD §4.6>. In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: Also, assume that instructions executed by the processor are broken down as follows: (a) What is the clock cycle time in a pipelined and non-pipelined processor? (b) What is the total latency of an lw instruction in a pipelined and non-pipelined processor? (c) If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? (d) Assuming there are no stalls or hazards, what is the utilization of the data memory? (e) Assuming there are no stalls or hazards, what is the utilization of the write-register port of the "Registers" unit? No hand written and fast answer with explanation