i) Construct a CMOS NAND gate, NMOS NAND gate and NMOS NOR gate. ii) What are the differences between Resistor Transistor Logic, Directly Coupled Transistor Logic and Transistor Transistor Logic? Draw 3 input NAND using RTL, 4 input NAND using DCTL. iii) A certain gate draws 3mA when its output is HIGH and its average power dissipation, Vcc is 7V for Transistor Transistor Logic. How much does the gate draw when its output is LOW? It draws 4.5 mA when in Transition time. Determine average power dissipation for CMOS. iv) Determine if the LSTTL (5V) can drive a CMOS (5V, HCT) circuit and vice versa. Voh Vol Vih S LSTTL 2.8 0.38 1.9 CMOS 2.3 0.75 2.85 Vil 0.9 0.75

Introductory Circuit Analysis (13th Edition)
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Author:Robert L. Boylestad
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Question
i) Construct a CMOS NAND gate, NMOS NAND gate and NMOS NOR
gate.
ii) What are the differences between Resistor Transistor Logic, Directly
Coupled Transistor Logic and Transistor Transistor Logic? Draw 3 input
NAND using RTL, 4 input NAND using DCTL.
iii) A certain gate draws 3mA when its output is HIGH and its average
power dissipation, Vcc is 7V for Transistor Transistor Logic. How much
does the gate draw when its output is LOW?
It draws 4.5 mA when in Transition time. Determine average power
dissipation for CMOS.
iv) Determine if the LSTTL (5V) can drive a CMOS (5V, HCT) circuit and
vice ve sa.
Voh
Vol
Vih
Vil
LSTTL
2.8
0.38
1.9
0.9
CMOS
2.3
0.75
2.85
0.75
Transcribed Image Text:i) Construct a CMOS NAND gate, NMOS NAND gate and NMOS NOR gate. ii) What are the differences between Resistor Transistor Logic, Directly Coupled Transistor Logic and Transistor Transistor Logic? Draw 3 input NAND using RTL, 4 input NAND using DCTL. iii) A certain gate draws 3mA when its output is HIGH and its average power dissipation, Vcc is 7V for Transistor Transistor Logic. How much does the gate draw when its output is LOW? It draws 4.5 mA when in Transition time. Determine average power dissipation for CMOS. iv) Determine if the LSTTL (5V) can drive a CMOS (5V, HCT) circuit and vice ve sa. Voh Vol Vih Vil LSTTL 2.8 0.38 1.9 0.9 CMOS 2.3 0.75 2.85 0.75
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