A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a maximum of 106 instructions per second. An average instruction requires five ma- chine cycles, three of which use the memory bus. A memory read or write operation uses one machine cycle. Suppose that the processor is continuously executing "background" programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is to be used to transfer very large blocks of data between M and D. a. If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in words per second, possible through D. b. Estimate the same rate if DMA is used.

A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word. The processor can execute a maximum of 106 instructions per second. An average instruction requires five ma- chine cycles, three of which use the memory bus. A memory read or write operation uses one machine cycle. Suppose that the processor is continuously executing "background" programs that require 95% of its instruction execution rate but not any I/O instructions. Assume that one processor cycle equals one bus cycle. Now suppose the I/O device is to be used to transfer very large blocks of data between M and D. a. If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in words per second, possible through D. b. Estimate the same rate if DMA is used.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

A 32-bit computer has 32 registers, and a memory addressed by bytes with two cycles for reading and writing operations. Consider the instruction ADD, R1, addr. This instruction adds the value stored in R1 to the value stored in the memory address addr, and stores the result in the register R1. a) Show a possible format for this instruction, having into account that the computer has 100 machine instructions and the addresses are represented using 32 bits. b) Indicate the elemental operations and control signals needed to execute the previous instruction.
Suppose the implementation of an instruction set architecture uses three classes of instructions, which are called A, B, and C. The total dynamic instruction count is 1 x 10^7 and the processor's clock rate is 2.5 GHz. Details for the three classes are given in the table below: Class CPI % of instructions A 1 20% 50% C 3 30% Complete the following table. Express all answers in scientific notation and round to two decimal places, when needed. Class Instruction Count Number of Clock Cycles х 10^ x 10^ A х 10^ х 10^ x 10^ х 10^ C
Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz.Computer B has a CPI of 2.5 and can be run at a clock rate of 750 Mhz. Wehave a particular program we wish to run. When compiled for computer A, thisprogram has exactly 100,000 instructions. How many instructions would theprogram need to have when compiled for Computer B, in order for the twocomputers to have exactly the same execution time for this program?
A certain microprocessor requires either 2, 3, 4, 8, or 12 machine cycles to perform various operations. A total of 25% of its instructions require 2 machine cycles, 20% require 3 machine cycles, 17.5% require 4 machine cycles, 12.5% require 8 machine cycles, and 25% require 12 machine cycles.Q) Suppose this system requires an extra 20 machine cycles to retrieve an operand from memory. It has to go to memory 40% of the time. What is the average number of machine cycles per instruction for this microprocessor, including its memory fetch instructions?
Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?
In this problem, you will explore processor frequency in the context of the speed of light.Suppose you have overclocked a processor to 8,722.78MHz. This processor can execute one instruction per cycle. Further let us suppose that the system is accessing a magnetic disk (HD) with an access time of 11ms. 1. Suppose that you are designing the machine architecture and want to guarantee the CPU can obtain data from memory within 4 CPU cycles. Given that the address has to travel from the CPU to the memory unit (MMU) and that the data has to travel from memory to the CPU, what is the maximum distance between CPU and the MMU if the signal on the memory bus propagates at 75% of the speed of light?
Q3) b There are two implementations; computer “A” with 1.75 GHz processor and 512 MB of RAM, while the processor speed of computer “B” is two times faster than A, i.e. 3.5GHz and similarly 1 GB of RAM. There is program with 10 instruction runs on A in 20ns while in the same period of time the another program with 20 instructions runs on B. Determine the CPUs performance and decide which one is faster.
hi can u anwser this qustion plesc ? Consider a Computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “K” addressing modes, and it has “M” computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory AddressGiven that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction.Note: Choose your own values for K (number of addressing modes) and M (number of Registers) k=8 m=50
Suppose that each of the 4 processors in a shared memory multi-processor system is rated at 400 MIPS. A program contains a purely sequential part that accounts for 22% of the program’s execution time on a single processor. The remaining code can be partitioned into three independent parts (A, B, and C). Running on a single processor, part A accounts for 30% of the program’s execution time, part B accounts for 18%, and part C accounts for 30%. What is the apparent MIPS rating for the program if it is run on the 4-processor system and the sequential part must be completed before any of the remaining independent parts (A, B or C) can run in parallel?
In this exercise, we examine in detail how much an instruction is executed in a single-cycle Datapath. The problem refers to a clock cycle in which the processor fetches the following instruction word: 1010 1100 0110 0010 0000 0000 0001 0100. Assume that data memory is all zeros and that the processor's registers have the following values at the beginning of the cycle in which of the instruction word is fetched: (See image attached) What is the new PC address after this instruction is executed? Highlight the path through which this value is determined?
5. Consider two microprocessors having 8- and 16-bit-wide external data buses, respectively. The two processors are identical otherwise and their bus cycles take just as long. (a) Suppose all instructions and operands are one byte long, by what factor do the maximum data transfer rates differ?
Question: Suppose a program of 600 instructions runs on a 2 GHz processor. The frequency of instructions and the clock cycle counts per instruction are given as follows. What is the average CPI of this instruction mix? Operation Frequency Clock Cycles ALU operations 55% 1 Loads/Stores 30% 2 Branches 15% 3 Question: Continue from the previous question. What is the CPU time of the program in nanoseconds? Question: Suppose a processor P has a 2.5 GHz clock rate and a CPI of 1.5. If the processor executes a program in 3 microseconds, find the number of instructions in the program.