(b) The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with four fields: an operation code field, a mode field to specify one of seven addressing modes, a register address field to specify one of 60 processor registers, and a memory address. Specify the instruction format and the number of bits in each field of the instruction if instruction is in one memory word.

(b) The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with four fields: an operation code field, a mode field to specify one of seven addressing modes, a register address field to specify one of 60 processor registers, and a memory address. Specify the instruction format and the number of bits in each field of the instruction if instruction is in one memory word.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

6. Assume that two numbers: dividend and divisor are saved in memory address M1 and M2 respectively. Quotient and remainder should be saved in R1 and R2 respectively. Write assembly language instructions and then list microoperations for each instruction and list the control signals required to be activated for each microoperation. MBR is used as buffer for any register to register transfer operation. Signal Description: Control signals operation Comments C0 MAR to RAM (through address bus) C1 PC to MBR C2 PC to MAR C3 MBR to PC C4 MBR to IR C5 RAM to MBR C6 MBR to ALU C7 Accumulator to ALU C8 IR to MAR C9 ALU to Accumulator C10 MBR to Accumulator C11 Accumulator to MBR C12 MBR to RAM (through data bus) C13 IR to Control Unit C14 MBR to R1 C15 MBR to R2 C16 MBR to R3 C17 MBR to R4…
6. Suppose that the interrupt processing method of is to store the breakpoint in the address of 00000Q unit, and fetch the instruction from the 77777Q unit (that is the first instruction of the interrupt service routine) and execute it. Write the micro-operations sequence that completes this function.
A large endian byte addressed memory system with eight distinct memory modules is included in a computer system. Each memory module has 134217728 cells and is 32 bits wide. a) What is the 32-bit memory address of cell 1048578 in module 3 if the memory uses high order interleaving? b) What is the 32-bit memory address of byte 1048575 inside module 2 if the memory uses high order interleaving? c) What is the 32-bit memory address of cell 511 inside module 1 if the high order interleaved memory utilises little endian storage order instead of big endian storage order?
Assume that the instruction pointer, EIP, contains 9810 and the assembly language representation of the instruction in memory at address 9810 is JAE 131. If the flags are currently CF=1, ZF=0 and SF=0 what is the value of the EIP after the instruction executes? The answer 102 is not correct so what is the correct answer?
Assume that the instruction pointer, EIP, contains 9810 and the assembly language representation of the instruction in memory at address 9810 is JAE 131. If the flags are currently CF=1, ZF=0 and SF=0 what is the value of the EIP after the instruction executes?
Suppose a machine has word length of 32 bits, and the CPU has 32 registers of 32 bits. Design an instruction system with 64 operations. (1) If it uses register addressing mode and the direct addressing mode in the instruction, what is the maximum main memory space that can be addressed? (2) What are the differences between the based index addressing and index addressing? (3) Introduce at least three of other addressing methods that can be used.
Consider a word-addressable computer with 32 bits per word. The instruction set consists of 30 different All instructions have an operation code field, a mode field to specify one of 7 possible addressing modes, a register address field to specify one of 60 available registers, and a memory address field. Each instruction is stored in one word of memory. What is the maximum allowable size for memory? Use KB, MB, or GB as a unit.
Consider a computer which has a memory which is capable of storing 4096 K words and each word in memory can be of size 32 bits. The computer supports a total of “8” addressing modes, and it has “50” computer registers. The computer supports instructions, where each instruction consists of following fields: Mode Operation code Register Register Memory Address Given that each instruction will be stored in one memory word, discuss with a suitable diagram the format of instruction by specifying number of bits for each field of instruction. Discuss each field of instruction
7-16. Add the following instructions to the computer of Sec 7-3 (EA is the effective address). Write the symbolic microprogram for each routine as in Table 7-2. (Note that AC must not change in value unless the instruction specifies a change in AC.) Symbol Opcode Symbolic Function Description AND 0100 AC ← AC ∧ M[EA] AND SUB 0101 AC ← AC - M[EA] Subtract ADM 0110 M[EA] ← M[EA] + AC Add to memory
computer architecture Assume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following a )What is the total cycle in single-cycle implementation? b )What is the total cycle in pipelining implementation? c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?
A computer system contains a big endian byte addressable memory system with 8 separate memory modules. Each memory module is 32 bits wide and contains 134217728 cells. Cells within each memory module are numbered 0 through 134217727. a) If the memory employs high order interleaving, what is the 32-bit memory address of cell 1048578 within module 3? b) If the high order interleaved memory uses little-endian instead of big-endian storage order, what is the 32-bit memory address of cell 511 within module 1? c) If the memory employs low order interleaving, what is the 32-bit memory address of byte 1048575 within module 2? Bytes are numbered starting from 0. Express the address in hex. d) What is the main advantage of using low-order interleaved memory compared to using high-order interleaved memory?
Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS fields: op = 0, rs = 16, rt= 15, rd = 22, shamt = 0, function = 34