Q3) If BP=1000, DS=0400, SS=0700, CS=0500 and AL=EDH, for the following instruction: MOV [BP] + 1234H, AL Find the physical address in the memory.
Q: if BX=1000, DS=0400, and AL=EDH, for the following instruction: MOV [BX] + 1234H, AL. the physical…
A: The answer will be:- 6234H
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Q: If BX=1000, DS=0200, SS=0100, CS=0300 and AL=EDH, for the following instruction: MOV [BX] + 1234H,…
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![Q3) If BP=1000, DS=0400, SS=0700, CS=0500 and AL=EDH, for the following
instruction:
MOV [BP] + 1234H, AL
Find the physical address in the memory.](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F4d777de0-cf99-40fe-9395-534da3fd7701%2F762ccf79-5e69-483d-9768-f5e0cbf8a1b7%2F7uinc35_processed.jpeg&w=3840&q=75)
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- Assume that CS=3500, DS=4500, SS=5500, SI=2200, DI=4200, BX=7300, BP=8000, AX=3420 (all values are in hex). Calculate the physical address of the memory and show the contents in each of the following: a) MOV [BP]+10,AX b) MOV [SI],AX c) MOV [BX][DI]+20,AXB) Amain memory address is viewed as consisting of multiple fields. List and define these fields for Direct Mapped Cache, Associative Mapped Cache and Set-associative Mapped Cache Memory.CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
- 3) Assume that there is a cache with 4 blocks and the block size is 1 byte (in total only 4B cache). The cache is initially empty. For two different configurations of the cache; direct-mapped and 2-way set associative, given memory addresses are accessed in the given order. Write if given addresses are hit or miss in the cache. address: 3 - 11 - 0 - 3 - 11As described in COD Section 5.7 (Virtual memory), virtual memory uses a page table to track the mapping of virtual addresses to physical addresses. This exercise shows how this table must be updated as addresses are accessed. The following data constitute a stream of virtual byte addresses as seen on a system. Assume 4 KiB pages, a four-entry fully associative TLB, and true LRU replacement. If pages must be brought in from disk, increment the next largest page number. TLB Page Table (a) For each access shown above, list whether the access is a hit or miss in the TLB, whether the access is a hit or miss in the page table, whether the access is a page fault, the updated state of the TLB. (b) Repeat Part a, but this time use 16 KiB pages instead of 4 KiB pages. What would be some of the advantages of having a larger page size? What are some of the disadvantages? (c) Repeat Part a, but this time use 4 KiB pages and a two-way set associative TLB. (d) Repeat Part a, but…Question 1 Consider the size of main memory as 32 Bytes and the size of cache memory as 8 Bytes. Implement the Set-Associative mapping technique. Do the following: a) Find the number of bits to address 32 bytes in main memory b) Write the formula to map block of main memory to set of cache memory c) Find the block size, line size, set size, tag size d) Draw the figure to show the distribution of main memory in desired blocks containing bytes e) Draw the figure to show the distribution of cache memory in desired lines containing tag numbers, respective blocks, and byte numbers f) Show the tag allocation for each set (and line) of cache memory
- Suppose a byte-addressable computer using set-associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.Q.) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the tag, set, and offset fields?CA_10 Let the virtual address be V bits and the virtual addtess space be byte-addressable, the page size be P KB (and P is a power of 2), and the the main memory size be MM MB(where [MM MB]) is divide into [P KB]). (d)How many of the virtual memory bits need to be translated? (e) How many bits will be produced if the virtual-to-pyysical address translation is "successful" (f) How many bits does a physical address have, and how are each of these bits obtained?Create a memory mapping from the cache memory of 512 MB to the main memory of 4 GB using the four-way set associative approach with a block size of 1 MB. Consider that each memory location may be accessed using a byte address.
- Suppose a computer using direct mapped cache has 232 byte of byte-addressable main memory, and a cache of 1024 blocks, where each cache block contains 32 bytes. a) How many blocks of main memory are there? b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag, block, and offset fields? c) To which cache block will the memory address 0x000063FA map?Computer Science Consider a direct-mapped cache with 8 lines, each holding 16 bytes of data. The cache is byte-addressable and the main memory consists of 64 KB, which is also byte-addressable. Assume that a program reads 16KB of memory sequentially. Answer the following questions:a) How many bits are required for the tag, index, and offset fields of a cache address?b) What is the cache size in bytes?c) What is the block size in bytes?d) What is the total number of blocks in main memory?e) How many cache hits and misses will occur for the program, assuming that the cache is initially empty?f) What is the hit ratio?g) Give an example virtual address (in BINARY) that will be placed in cache line 5.Assume the following values are stored at the indicated memory addresses and registers Address Value 0x100 0xaaa 0x104 0x123 0x108 0x12 0x10c 0x10 Register Value %eax 0x100 %ecx 0x1 %edx 0x3 Fill up the following table: %eax 0x104 $0x108 (%eax) 4(%eax) 9(%eax,%edx) 260(%ecx,%edx) 0xFC(,%ecx,4) (%eax,%edx,4)