Briefly answer the following questions: a) List at least 5 SFRs in PIC18F87J11. b) Given an instruction example for each addressing mode in PIC18F87J11. c) Describe and draw the memory architecture for PIC18F87J11
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Briefly answer the following questions:
a) List at least 5 SFRs in PIC18F87J11.
b) Given an instruction example for each addressing mode in PIC18F87J11.
c) Describe and draw the memory architecture for PIC18F87J11
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- Describe and compare the characteristics of TTL and CMOS Logic families. Please don't write on paperDraw the figure for memory segments with 8086 microprocessor software model. Explain the logical address structure used for each segment (Explain which registers are used in logical address presentation of each segment; segment address : offset address). Give an example solution to find the physical address in a segment from the logical address for 8086 microprocessor.Use the graphical technique described in the EIA to find the noise margins for the standard TTL gate.
- 5) below is the accuracy table showing the output values for two separate binary number entries (W and Y) with a length of two bits. Get the simplest form of output functions with the Karnaugh diagram. Draw a logic diagram of the circuit that performs the function of these functions.Describe in detail which functions a, b and C perform for 2-bit binary numbers in the input.23/ Name the logic family which implements LSI and VLSI digital functions. A) CMOS Logic B) Integrated Injection Logic C) Transistor-Transistor Logic D) Emitter coupled LogicWrite an assembly language program for 8085 microprocessor to add 2 digit BCD numbers stored in memory location C050H and C051H respectively and store the result in memory location C052H.
- Define a 2-bit demultiplexer to be a circuit whose single input line is steered to one of the four output linesdepending on the state of the two control lines (A, B). Draw its logic diagram (to the gate level) and specify the exactstate of A and B for each output line when that output line is selected.The initial state of the four-bit synchronous binary addition counter Q3Q2Q1Q0 is 1100. After 8 CP clock pulses, its state Q3Q2Q1Q0 changes to ----?Design 3 systems that represent minterm 30 for a 5-input system: 1.-using logic gates, with a maximum of two inputs each, which represent a low active output. Ensures efficient interpretation of the diagram 2.- exclusively using two-input NAND logic gates 3.- Using components at TTL level.
- A 4 bit binary count have terminal count of?With a neat logic diagram and shifting table, explain the shifting of given bit stream 1011001 entered from LSB in serial –in-serial-out 4 bit shift right register. Also mention after how many clock pulses, MSB is retrieved.19. With necessary diagrams and equations, describe the operation of different types of single-phase PWM inverters. Compare multiple-pulse and sinusoidal pulse modulation schemes with single-phase PWM scheme.