byte offset of 2 in an address means that each set in a multiway set associative (or in the directly mapped) cache has 4 bytes per set, per cache line. Keeping this in mind, answer the questions given the following details. A cache is organized as a 4 way set associative cache Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache). Each set individually has one Valid bit, and one Dirty bit, for each line. The tag field of this cache is 8 bits wide. The address is 32 bits wide. Question 1a) What is the number of cache lines? Question 1b) What is the total number of 'memory bitcells' that are needed to design this cache (note, this includes the bitcells required for the tags, valid and dirty bits). Question 1c) What is the cache size? (Meaning the number of kilobytes of data being stored in this cache, ignoring the tag, dirty, and valid bits) Question 1d) If this same sized cache (meaning the number of kilobytes of the data part from the question 1c above) are instead organized as a direct mapped cache, what is the total number of 'memory bitcells' needed to design this cache instead (meaning how many bitcells including the tag, dirty, and valid bits? (Assume that the number of cache lines are not changing and that all the bytes of all four sets are now coalesced into one set, thus making it a direct mapped cache) Question 1e) Which implementation of the cache (4-way set associative or the direct mapped cache) would you guess will take more power when we do one read? (Think of how many number of devices/memory cells will be needing to do 'work' in each of the designs, and explain your answer accordingly) Question 1f) In which of these implementations can LRU be used as a replacement policy? Question 1g) If we have a write through cache coherency policy, will either of the above organizations make a difference in the amount of power used to do one write through operation (specifically above this cache layer, in the upper level memory structures to maintain coherency. The question is now saying which organization will result in a large number of operations, but when an operation is taking place would it matter what the structure was)? Explain your answer cri
A byte offset of 2 in an address means that each set in a multiway set associative (or in the directly mapped) cache has 4 bytes per set, per cache line. Keeping this in mind, answer the questions given the following details.
A cache is organized as a 4 way set associative cache
Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache).
Each set individually has one Valid bit, and one Dirty bit, for each line.
The tag field of this cache is 8 bits wide.
The address is 32 bits wide.
Question 1a) What is the number of cache lines?
Question 1b) What is the total number of 'memory bitcells' that are needed to design this cache (note, this includes the bitcells required for the tags, valid and dirty bits).
Question 1c) What is the cache size? (Meaning the number of kilobytes of data being stored in this cache, ignoring the tag, dirty, and valid bits)
Question 1d) If this same sized cache (meaning the number of kilobytes of the data part from the question 1c above) are instead organized as a direct mapped cache, what is the total number of 'memory bitcells' needed to design this cache instead (meaning how many bitcells including the tag, dirty, and valid bits? (Assume that the number of cache lines are not changing and that all the bytes of all four sets are now coalesced into one set, thus making it a direct mapped cache)
Question 1e) Which implementation of the cache (4-way set associative or the direct mapped cache) would you guess will take more power when we do one read? (Think of how many number of devices/memory cells will be needing to do 'work' in each of the designs, and explain your answer accordingly)
Question 1f) In which of these implementations can LRU be used as a replacement policy?
Question 1g) If we have a write through cache coherency policy, will either of the above organizations make a difference in the amount of power used to do one write through operation (specifically above this cache layer, in the upper level memory structures to maintain coherency. The question is now saying which organization will result in a large number of operations, but when an operation is taking place would it matter what the structure was)? Explain your answer crisply.
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