Consider a system with 36-bit virtual addresses, 32-bit physical addresses, and 4KB pages. The system uses a page table to translate virtual addresses to physical addresses; each page table entry Virtual Page Number (VPN) Valid Bit (V) Dirty Bit (D) PPN(Physical Page Number) include dirty (D) and resident (R) bits. Translation Look aside Buffer (ILB) Tag 00000A in HEX 0000A a) Assuming a flat page table, what is the size of each page table entry, and how many entries does the page table have? b) If you changed the system to use 1KB pages instead of 4 KB pages, how would the number of entries in the page table change? Please give the ratio of the new size to the old size. c) For page size of 4KB, the contents of the page table and TLB are shown to the right. The page table uses an LRÚ replacement policy, and the LRU page (shown below) will be chosen for replacement. For each of these four accesses, compute its corresponding physical address and indicate whether the access causes a TLB miss and/or a page fault. Assume each access starts with the TLB and Page Table state shown to the right. 000016 1 7390E 000009 1230A 000001 12300 1 1 000023 A390E 000007 1 1 A1215 000010 00000E Page Table 0001C 1 1 |756AC Virtual Page Number (VPN) Resident Bit (R) Dirty Bit (D) PPNPhysical Page Number) in HEX in HEX Fill in Table below VA(Virtual TLB Page PPN(Physical Page PA (Physical Fault? 1 12300 Address) in HEX Address) in HEX 00000E 000016 000007 Miss? (Y/ N) Number) in HEX (Y/ N) 3 1 23А21 4 5 1 9812A 6. 1 1 00000A 1 50200 000011 7 1 A1215 8 00000C 000001 9 000009 A OA521 000010 B 1 B2178 000003 D - E 1 1 756AC F 10 1 3141F

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Author:James Kurose, Keith Ross
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Consider a system with 36-bit virtual addresses, 32-bit physical addresses, and 4KB pages. The Translation Look aside Buffer (TLB)
system uses a page table to translate virtual addresses to physical addresses; each page table entry
include dirty (D) and resident (R) bits.
8.
Virtual Page Number (VPN) Valid Bit (V) Dirty Bit (D) PPN(Physical Page Number)
Tag
00000A.
in HEX
0000A
a) Assuming a flat page table, what is the size of each page table entry, and how many entries
does the page table have?
b) If you changed the system to use 1KB pages instead of 4 KB pages, how would the number of
entries in the page table change? Please give the ratio of the new size to the old size.
c) For page size of 4KB, the contents of the page table and TLB are shown to the right. The
page table uses an LRU replacement policy, and the LRU page (shown below) will be chosen
for replacement. For each of these four accesses, compute its corresponding physical address
and indicate whether the access causes a TLB miss and/or a page fault. Assume each access
starts with the TLB and Page Table state shown to the right.
000016
1
7390E
000009
1230A
000001
1
12300
000023
1
1
A390E
000007
1
1
A1215
00001C
0001C
00000E
Page Table
Virtual Page Number (VPN) Resident Bit (R) Dirty Bit (D) PPNPhysical Page Number)
1
1
756AC
in HEX
in HEX
Fill in Table below
VA(Virtual
PA (Physical
Address)
in HEX
TLB
PPN(Physical Page
Page
Fault?
Miss?
1
1
12300
Address)
in HEX
Number)
in HEX
2
(Y/ N)
(Y / N)
00000E
3
1
1
23А21
4
000016
000007
5
1
9812A
6.
1
1
50200
00000A
7
1
1
A1215
000011
00000C
9
000001
000009
000010
-
A
1
ОА521
B
1
B2178
000003
-
D
E
1
1
756AC
F
1
3141F
10
51718
6721A
11
1
12
1
13
1
1
OAOBC
14
1
1
100AB
15
1
1
80AB1
16
7390E
Transcribed Image Text:Consider a system with 36-bit virtual addresses, 32-bit physical addresses, and 4KB pages. The Translation Look aside Buffer (TLB) system uses a page table to translate virtual addresses to physical addresses; each page table entry include dirty (D) and resident (R) bits. 8. Virtual Page Number (VPN) Valid Bit (V) Dirty Bit (D) PPN(Physical Page Number) Tag 00000A. in HEX 0000A a) Assuming a flat page table, what is the size of each page table entry, and how many entries does the page table have? b) If you changed the system to use 1KB pages instead of 4 KB pages, how would the number of entries in the page table change? Please give the ratio of the new size to the old size. c) For page size of 4KB, the contents of the page table and TLB are shown to the right. The page table uses an LRU replacement policy, and the LRU page (shown below) will be chosen for replacement. For each of these four accesses, compute its corresponding physical address and indicate whether the access causes a TLB miss and/or a page fault. Assume each access starts with the TLB and Page Table state shown to the right. 000016 1 7390E 000009 1230A 000001 1 12300 000023 1 1 A390E 000007 1 1 A1215 00001C 0001C 00000E Page Table Virtual Page Number (VPN) Resident Bit (R) Dirty Bit (D) PPNPhysical Page Number) 1 1 756AC in HEX in HEX Fill in Table below VA(Virtual PA (Physical Address) in HEX TLB PPN(Physical Page Page Fault? Miss? 1 1 12300 Address) in HEX Number) in HEX 2 (Y/ N) (Y / N) 00000E 3 1 1 23А21 4 000016 000007 5 1 9812A 6. 1 1 50200 00000A 7 1 1 A1215 000011 00000C 9 000001 000009 000010 - A 1 ОА521 B 1 B2178 000003 - D E 1 1 756AC F 1 3141F 10 51718 6721A 11 1 12 1 13 1 1 OAOBC 14 1 1 100AB 15 1 1 80AB1 16 7390E
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