Consider a system with 64-bit address that supports multi-level page tables with two levels. The page size is 16KB and each page table entry (PTE) is 8B. PTE1# PTE2# offset How many bits are used for PTE1, PTE2 and the offset in the virtual address?
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- Consider a computer which uses virtual addressing with 32 bit addresses and a two level page table. The virtual addresses are split into a 9 bit top level page table field, an 11 bit second level page table field and an offset. How large are the pages and, how many are there in the address space?A computer with a 32-bit address uses a two-level page table. Virtual addresses are split into a 9-bit top-level page table field, an 11-bit second-level page table field, and an offset. How large are the pages and how many are there in the address space?Consider a system with the following specifications: 46-bit virtual address space Page size: 8 KB Page table entry size (PTE): 4 bytes How many levels should a multi-level page table have, if the page table at each level must fit into a single page ? Explain.
- Suppose that a machine has 38-bit virtual addresses and 32-bit physical addresses.(a) What is the main advantage of a multilevel page table over a single-level one?(b) With a two-level page table, 16-KB pages, and 4-byte entries, how many bits should be allocated for the top-level page table field and how many for the next-level page table field? Explain.On a simple paging system with 224 bytes of physical memory, 256 pages of logical address space, and a page size of 210 bytes. 1. How many bits are needed to store an entry in the page table (how wide is the page table)? Assume a valid/invalid 1-bit is included in each entry. 2. If the page table is stored in the main memory with 250nsec access time, how long does a paged memory reference take? 3. If the page table is implemented using associative registers that takes 95nsec. and main memory that takes 200nsec, what is the total access time if 75% of all memory references find their entries in the associative registers?A computer with 32 bits virtual address uses a two-level page table. Virtual addresses are split into a 10 bits top-level page table field (PT1), a 10 bits second-level page table field (PT2), and an offset. How many PT1, PT2, and offset with virtual address 0x00403008? A. PT1=1; PT2=1; offset=8B. PT1=1; PT2=3; offset=8C. PT1=4; PT2=3; offset=8D. PT1=4; PT2=1; offset=8
- Suppose we have a virtual address of 26 bits in a byte addressable machine. Page size is 8K bytes. Assume each page table entry is 4 bytes in this case. a. Design a two-level page table (Suppose we need to fit each page table into a physical frame). b. How many physical memory frames are needed to maintain the page tables for a process of 512KB?Consider a paging system with the following: Physical memory= 32 bytes. Page size=4 bytes. Page Table: Page Frame 0 5 1 6 2 1 3 2 What are the physical addresses for the following logical addresses? A) 15 B) 8 C) 4Assume a 32-bit address system that uses a paged virtual memory, with a page size of 2 KB, and a PTE (Page Table Entry) size of 1 B. Answer the following questions, assuming a virtual address 0x00030f40 a. What is the virtual page number (VPN) and the offset in binary for the given virtual address? b. How many virtual pages are there in the system?
- Suppose that a machine has 42-bit virtual addresses and 32-bit physical addresses.{a} How much RAM can the machine support (each byte of RAM must be addressable)?{b} What is the largest virtual address space that can be supported for a process?{c} If pages are 2 KB, how many entries must be in a single-level page table?{d} If pages are 2 KB and we have a two-level page table where the first level is indexed by 15-bits, then how many entries does the first-level page table have?{e} With the same setup as part {d}, how many entries are in each second-level page table?{f} What is the advantage of using a two-level page table over single-level page table?Consider a paging system with the page table stored in memory.a. If a memory reference takes 400 nanoseconds, how long does a paged memoryreference take?b. If we add TLBs, and 95 percent of all page-table references are found in the TLBs,what is the effective memory reference time? (Assume that finding a page-table entry inthe TLBs takes zero time, if the entry is there.)In an architecture with 18 bits of "virtual address" width, "page size" is given as 1024 bytes and "physical address" width is given as 15 bits. TLB has a “2-way set associative” structure and contains a total of 16 data blocks. What is the TLB Tag field width in this architecture? A) 4 B) 5 C) 6 D) 7 E) 8