Considering direct mapping, associative mapping and 4-way set associative mapping techniques. a. How can you increase the hit ratio in case of direct mapping by changing some of size of Caches? b. Give reasons why the hit ratio increases when you change the size of caches? c. Explain the reason for the number of bits being used for Tag and for the number of bits required for RAM address?

Considering direct mapping, associative mapping and 4-way set associative mapping techniques. a. How can you increase the hit ratio in case of direct mapping by changing some of size of Caches? b. Give reasons why the hit ratio increases when you change the size of caches? c. Explain the reason for the number of bits being used for Tag and for the number of bits required for RAM address?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Describe the differences between sequential access, direct access and random access? How does the principle of locality relate to the use of multiple memory levels What are the differences between direct mapping, associative mapping and set associative mapping? What are the three fields of main memory associated with a direct mapped cache? What are the two fields of main memory associated with an associative cache? What is the difference between special locality and temporal locality? What are the general strategies for using spacial locality and temporal locality?
Make the difference between a cache that is directly mapped and one that is totally associative.
Consider a computer with 128 MB of main memory, 64 KB of cache, and 4 bytes per memory block. Find out how to split the address (s-r, r, w) so that it can be used for direct mapping.Find out how to split the address into two parts (s and w) for associative mapping.Find out how to split the address into three parts (s-d, d, and w) for set associative mapping. Assume that each cache set has two lines.
What are some of the reasons why it is difficult to create a cache replacement policy that is optimal for all address sequences?
Take into account the following scenario: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Since there are 8 bytes in a block, you can use that information to calculate how big the offset field has to be.
CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
Discuss in detail the type of mapping technique in which each word of cache can store two or more words of memory under the same index address. Support your answer with a neat and clean diagram.
Describe why it is difficult to implement a cache replacement policy that is optimal for all address sequences.
For a direct-mapped cache design with a 32-bit address, the following bits of the address areused to access the cache.Tag Index Offset31–10 9–6 5–0a– What is the cache block size (in words)? b – How many entries does the cache have? c – What is the ratio between total bits required for such a cache implementation overthe data storage bits?
Q. Consider a system with 4-way set associative cache of 256 KB. The cache line size is 8 words (32 bits per word). The smallest addressable unit is a byte, and memory addresses are 64 bits long. (a) How many bits are used for TAG and INDEX fields of cache mapping?
A byte-addressable system with 16-bit addresses ships with a three-way set associative, write-backcache (i.e., each block needs a dirty bit). The cache implements a true LRU replacement policy usingthe minimum number of replacement policy bits necessary to implement it, which means it requires 3bits per set. The tag store requires a total of 264 bits of storage. What is the block size of the cache?(Hint: 264 = 2^8 + 2^3 and please also do not forget that aside from the tag itself, each block needs 1valid bit, 1 dirty bit).
Assume a direct-mapped cache that holds 4096 bytes, in which each block is 16 bytes. Assuming that an address is 32 bits and that cache is initially empty, complete the table that follows.(You should use hexadecimal numbers for all answers.) Which, if any, of the addresses will cause a collision (forcing the block that was just brought in to be overwritten) if they are accessed one right after the other?