Consider a 2-way set associative cache with 32-bit address. The block offset takes 5 bits, the index takes 5 bits. Starting from power on, the following byte-addressed cache references are recorded. Address 4. 16 132 232 160 1024 30 140 3100 180 2180 1. What is the cache capacity? (number of bytes) 2.What is the status for each access? (hit, miss and replacement). 3.What is the hit ratio?

Consider a 2-way set associative cache with 32-bit address. The block offset takes 5 bits, the index takes 5 bits. Starting from power on, the following byte-addressed cache references are recorded. Address 4. 16 132 232 160 1024 30 140 3100 180 2180 1. What is the cache capacity? (number of bytes) 2.What is the status for each access? (hit, miss and replacement). 3.What is the hit ratio?

Enhanced Discovering Computers 2017 (Shelly Cashman Series) (MindTap Course List)

1st Edition

ISBN:9781305657458

Author:Misty E. Vermaat, Susan L. Sebok, Steven M. Freund, Mark Frydenberg, Jennifer T. Campbell

Publisher:Misty E. Vermaat, Susan L. Sebok, Steven M. Freund, Mark Frydenberg, Jennifer T. Campbell

Chapter6: Computing Components: Processors, Memory, The Cloud, And More

Section: Chapter Questions

Problem 21CT

See similar textbooks

Similar questions

For a direct-mapped cache design with a 32-bit address, the following bits of the address areused to access the cache.Tag Index Offset31–10 9–6 5–0a– What is the cache block size (in words)? b – How many entries does the cache have? c – What is the ratio between total bits required for such a cache implementation overthe data storage bits?
Consider a cache with the following parameters: N (associativity) = 2, b (block size) = 2 words, W (word size) = 32 bits,C (cache size) = 32 K words, A (address size) = 32 bits. You need consider only word addresses.(a) Show the tag, set, block offset, and byte offset bits of the address. State how many bits are needed for each field.(b) What is the size of all the cache tags in bits?(c) Suppose each cache block also has a valid bit (V) and a dirty bit (D). What is the size of each cache set, including data, tag, and status bits?(d) Design the cache using the building blocks in Figure 8.28 and a small number of two-input logic gates. The cache design must include tag storage, data storage, address comparison, data output selection, and any other parts you feel are relevant. Note that the multiplexer and comparator blocks may be any size (n or p bits wide, respectively), but the SRAM blocks must be 16K × 4 bits. Be sure to include a neatly labeled block diagram. You need only design the…
Consider a direct-mapped cache memory with 12-bit addresses. The cache is byte-addressable. We have B = 16 bytes per block and S = 8 sets. For the address shown below. Indicate which bits correspond to the cache set index, tag bits, and block offset. Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Consider a direct mapped cache that holds 1024 words, has a block size of one word, and uses 32-bit addresses. How many bits are in the tag? Please break the steps with explanations
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.Tag Index Offset31–10 9–5 4–01. What is the cache block size (in words)?2. How many entries does the cache have?3. What is the ratio between total bits required for such a cache implementation over the data storage bits?Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 How many blocks are replaced? What is the hit ratio? List the fi nal state of the cache, with each valid entry represented as a record of <index, tag, data>
Consider a cache with a line size of 32 bytes and a main memory that requires 30 ns to transfer a 4-byte word. For any line that is written at least once before being swapped out of cache , what is the average number of times that the line must be written before being swapped out for a write back cache to be more efficient that a write-through cache?
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache: Tag Index Offset 31-10 9-6 5-0 1. What is the cache block size (in words)? 2. How many entries does the cache have? 3. What is the ratio between total bits required for such a cache implementation over the data storage bits?
Suppose a computer using set associative cache has 221 words of main memory and a cache of 64 blocks, where each cache block contains 4 words. a)If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and word fields? b)If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Consider a 4-way set associative cache made up of 64-bit words. The number of words per line is 8 and the number of sets 4096 sets. What is the cache size? a) 1 MB b) 10 MB c) 4 MB d) 512 MB
Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
For a direct-mapped cache design with a 32-bit address, the following bitsof the address are used to access the cache. Use the table below. a. What is the cache block size (in words)?b. How many entries does the cache have?c. What is the ration between total bits required for such a cache implementation overthe data storage bit?