design a 3-bit squarer circuit (b2 b1 b0)2example if input is 4 so the output will be 4^2=16 The following truth table represents the outputs and the inputs for 3-bit squarer circuit where b2,b1,b0 are the inputs and P5 (MSB) .P4,P3,P2,P1,PO (LSB) are the outputs Find the equation for PO Select one: O a. P4=b2b1' O b. P4=b2b1'+b2 O C. P4=b2b1'+b2b0 O d. P4=b2b1'+b2b0'
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- Consider a special purpose decoder that is called BCD to seven-segment decoder. The decoder takes a 4-bit Binary Coded Decimal (BCD) number X3 X2 X4 X0 (0-9) and produces 7 outputs a, b, c, d, e, f, and g The specification of this circuit is as follows: ⚫ The 7 outputs of the decoder are connected to LED segments as shown in the figure below. The LEDs are active low, ie, the LED emits light when it is connected to logic 0. • The decoder output is determined in a way so that the LED segments display the decimal representation of the input. For example, if the input X3 X2 X1 X0 is 0001 respectively (which is equivalent to decimal 1), the outputs a, b, c, d, e, f, and gare 1001111 showing the letter 1 on the display (remember the LEDs are active low). Decoder W- 4x7 e U Answer the following questions: a. Fill in the truth table of that decoder. Choose a good value for the output when the input is greater than decimal 9. b. Derive the simplified Boolean expressions for the outputs a, b, c,…Design a circuit that takes three bits, X2, X1, X0 as input and produces one output, F. F is 1 if and only if 2<=X<=5 when X = (X2, X1, X0) is read as an unsigned integer. For example, if X2=1, X1=0, and X0=0, then the unsigned binary value is 100, which is 4, so the output would be 1. Your Assignment For This Problem Includes the Following Design the necessary circuit using Logisim to implement the situation described above. Use Kmaps for simplification. Be VERY careful to get the correct functions for your output before simplifying and designing the circuit with Logisim. You should minimize the circuit. Your circuit should have three inputs and one LED output. All inputs (X2, X1, X0) and output (F) should be labeled (in Logisim, not by hand). Please use these names to indicate the inputs and output so all projects are consistent. You should also include your name as a label on the circuit. Test your circuit to be sure it is working correctly.Design a 2-bit binary full-adder circuit using a true-output decoder. Assume carry input of the 2-bit binaryfull-adder is zero.Circuit adds two 2-bit binary numbers A, consisting of bits A1, A0, and B, consisting of bits B1, B0. Thesum that is produced by the adder circuit consists of two sum bits S1, S0 and a carry out bit C0.Provide:i. Boolean equations for S1, S0 and C0.ii. Completely labelled logic diagram of decoder that implements the required operation.(You can represent the decoder in form of block diagram)
- 4 bit 2’s Complement Multiplier INPUT A: 4 bit 2’s Complement numberINPUT B: 4 bit 2’s Complement numberOUTPUT: the product of A x B represented as a 8 bit 2’s Complement number Do this:Build a 4 Bit UNSIGNED Multiplier as a subcircuit named UnsignedMultiplier use AND gate ,full and half adders for the circuitDesign a circuit that has two inputs X, and S, where X represents an 8-bit BCD number, S is a sign bit. The circuit has one output Y, which is the Binary representation of the signed-magnitude BCD number. A negative output is represented in the Binary 2’s- complement form. You need to think of two design alternatives. Submission guidelines: 1. You should write a report that at least contains the following sections: 1. Problem definition. 2. Design alternatives : 2.1. Alternative 1 block diagram 2.2. Alternative 2 block diagram 3. Design selection criteria 4. Detailed circuit design of the selected alternative. 5. Verilog modules, and simulation results for all modules, and for the whole circuit of the selected alternative .Design a 2-bit binary full-adder circuit using a true-output decoder. Assume carry input of the 2-bit binary full-adder is zero. Circuit adds two 2-bit binary numbers A, consisting of bits A1, AO, and B, consisting of bits B1, BO. The sum that is produced by the adder circuit consists of two sum bits S1, SO and a carry out bit CO. Provide:i. Boolean equations for S1, SO and Co.ii. Completely labelled logic diagram of decoder that implements the required operation. (You can represent the decoder in form of block diagram)
- 6. For the showa device, determine the output for the inputs 0110 , \[ \$ 1=1, S 0=1 \text {, and Enable }=0 . \] A. 1 . B. 0. C. Hj-Z. D. Don't Care. 7. Implement the Half-Adder circuit (S and C) with a decoder (use a block diagram for the Decoder) and the minimum number of gates. 8. Design a combinational circuit with three inputs and the output is 1 when the binary value of the inputs is greater than 4 . The output is 0 otherwise In yowr design, you have to do the three steps of the design procedures as follows: - Derive the truth table - Reduce the circuit using K-map - Draw the resultant logic circuit. 9. Use the dawa 8-to-1 multiplexer w implewest the functionfrepersented by the following truth wable. Please give proper explanation and typed answer only.Design an unsigned 8-bit divide-by-ten circuit which gives the output as Quotient and Remainder. The design should contain different modules for data path & control path. Paperwork should contain algorithms and block diagrams with all control signals which you have used in your design. If you are using FSM in your code , then write it in paperwork. To test the design take input as the last three digits i.e 009 and convert in binary. Then divide it by 10.4 bit 2’s Complement Multiplier INPUT A: 4 bit 2’s Complement number INPUT B: 4 bit 2’s Complement number OUTPUT: the product of A x B represented as a 8 bit 2’s Complement number PART 3: Build a 4 Bit UNSIGNED Multiplier as a subcircuit named UnsignedMultiplier use AND gate ,full and half adders for the circuit
- . Given the function: F(a, b, c) = (a + b)’c + a b c’ + a c a) Create the truth table for function F. 7b) Implement F by means of an 8-to-1 Multiplexer using block diagrams. Implement F by means of a 3-to-8 Decoder using block diagrams and any gates if needed.Design a 4-bit arithmetic circuit, with two selection variables S1 and S0, that generates the arithmetic operations in the following table. Draw the logic diagram for a single bit stage. Note that B’ represents “Not B”. Please write down an optimized equation for Xi and Yi,Design the simplest circuit that has three inputs, a, b, and c, which returns an output value of 1 whenever g and b are complements of each other or b and c are complements of each other, otherwise the output is 0. Realize the circuit using 4input , 3output PAL