Design a synchronous BCD Counter based on the following conditions. Design the Down counter with JK-Flip Flops by initializing the counter with 3 and count next five states. The counter should cycle back after counting five states. Perform all necessary designing steps

asynchronous counters differs from a synchronous counter in *     (a) the number of state in sequence     (b) the method of clocking     (c) the type of flip-flops used     (d) the value of the modulus

7. Draw a logic diagram for a 5-bit ring counter has an initial state 01011 and determine the waveform for each Q output during 5 clock pulses.

5. JK flip-flops are often used to build counters. The JK flip-flop will toggle the original output value when triggered by the clock signal if both the J,K inputs are connected with a constant "high"(logic 1). All the JK flip-flops in Figure 2 are negative edge triggered. All the initial values of Q2Q1Q0 are 0. Qo (LSB) (MSB) Input K K Logic 1 Input Q2 000 Figure 2. Counter (a) Sketch the output waveforms forQ2 Q1 Q0. Write down the output binary value (Q2Q1Q0: such as "000", "001") for each clock period on the figure. (b) Describe the function of the counter (e.g. binary down counter counting from 7 to 0).