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Design a verilog code for a sequential circuit which has two inputs, w1 and w2, and an output, z. Its function is to compare the input sequences on the two inputs. If w1 = w2 during any four consecutive clock cycles, the circuit produces z = 1; otherwise, z = 0. For example w1 :     0 1 1 0 1 1 1 0 0 0 1 1 0 w2 :     1 1 1 0 1 0 1 0 0 0 1 1 1 z :         0 0 0 0 1 0 0 0 0 1 1 1 0

Design a verilog code for a sequential circuit which has two inputs, w1 and w2, and an output, z. Its function is to compare the input sequences on the two inputs. If w1 = w2 during any four consecutive clock cycles, the circuit produces z = 1; otherwise, z = 0. For example w1 :     0 1 1 0 1 1 1 0 0 0 1 1 0 w2 :     1 1 1 0 1 0 1 0 0 0 1 1 1 z :         0 0 0 0 1 0 0 0 0 1 1 1 0

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Design a verilog code for a sequential circuit which has two inputs, w1 and w2, and an output, z. Its function is to compare the input sequences on the two inputs. If w1 = w2 during any four consecutive clock cycles, the circuit produces z = 1; otherwise, z = 0. For example

w1 :     0 1 1 0 1 1 1 0 0 0 1 1 0
w2 :     1 1 1 0 1 0 1 0 0 0 1 1 1
z :         0 0 0 0 1 0 0 0 0 1 1 1 0
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