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- Processor R is a 64-bit RISC processor with a 2 GHz clock rate. The average instruction requires one cycle to complete, assuming zero wait state memory accesses. Processor C is a CISC processor with a 1.8 GHz clock rate. The average simple instruction requires one cycle to complete, assuming zero wait state memory accesses. The average complex instruction requires two cycles to complete, assuming zero wait state memory accesses. Processor R can’t directly implement the complex processing instructions of Processor C. Executing an equivalent set of simple instructions requires an average of three cycles to complete, assuming zero wait state memory accesses. Program S contains nothing but simple instructions. Program C executes 70% simple instructions and 30% complex instructions. Which processor will execute program S more quickly? Which processor will execute program C more quickly? At what percentage of complex instructions will the performance of the two processors be equal?Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3.1 GHz clock rate and a CPI (cycles per instruction) of 1.6. P2 has a 2.4 GHz clock rate and a CPI of 1.2. P3 has a 4.0 GHz clock rate and has a CPI of 2.0 If you could answer these id appreciate that greatly. a.Which processor has the highest performance expressed in instructions per second? b.If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions. c.We are trying to reduce the execution time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction?Let's assume that there are three processors, Pa, Pb, and Pc, like below. You can assume 1-way superscalar, no hyper-threading, and no pipelined for all processors. Pa: 4 GHz clock rate, CPI: 2.2 Pb: 3 GHz clock rate, CPI: 1.5 Pc: 2.5GHz clock rate, CPI: 1.05.1. Show each processors' performance in terms of instruction per second.
- Consider three different processors P1, P2, and P3 executing the same instructionset. P1 has a 3GHz clock rate and a CPI of 1.5. P2 has a 2.5GHz clock rate and a CPI of 1.0, P3has a 4GHz and a CPI of 2.5.a) Which processor has the highest performance expressed in instructions per second?b) If the processors each execute a program in 5 seconds, find the number of cycles and thenumber of instructions.c) We are trying to reduce the execution time by 20% but this leads to an increase of 15% inthe CPI. What clock rate should we have to get this time reduction?Consider three different processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. Which processor has the highest performance expressed in instructions per second? If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions.Q: Consider three different processors P1, P2, and P3 that support the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2. (a) Which processor has the highest performance expressed in instructions per second? Show your calculations. (b) If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions for each processor. (c) We are trying to reduce the execution time by 30% (i.e., execution time is reduced from 10 seconds to 7 seconds). However, this leads to an increase of 20% in the CPI. For each processor, what clock rate should we have to get this time reduction? (Show the calculations you did to answer this question.)
- Consider three different processors P1, P2, P3 executing the same set of instructions. P1has a 3 GHz clock rate and a CPI of 1.5. P2 runs at 2 GHz and has a CPI of 1.2. P3 has a 4GHz clock rate and a CPI of 2.4.a. Which processor has the highest performance in terms of instructions per second?b. If each processor executes a program in 5 second, find the number of cycles and thenumber of instructions for each processor.c. We would like to reduce the execution time by 20%. This will, however, increasethe CPI by 25%. What clock rate do we need to obtain this amount of timereduction?Question: Suppose a program of 600 instructions runs on a 2 GHz processor. The frequency of instructions and the clock cycle counts per instruction are given as follows. What is the average CPI of this instruction mix? Operation Frequency Clock Cycles ALU operations 55% 1 Loads/Stores 30% 2 Branches 15% 3 Question: Continue from the previous question. What is the CPU time of the program in nanoseconds? Question: Suppose a processor P has a 2.5 GHz clock rate and a CPI of 1.5. If the processor executes a program in 3 microseconds, find the number of instructions in the program.Consider an unpipelined processor. Assume that it has 1-ns clock cycle and that it uses 4 cycles for ALU operations, and 5 cycles for branches, and 4 cycles for memory operations. Assume that the relative frequencies of these operations are60%,20%, and20%respectively. Suppose that due to clock skew set up, pipelining the processor adds0.2 nsof overhead to the clock. Ignoring any latency impact, how much speed up in the instruction execution rate will we gain from a pipeline? Please type answer no write by hend.
- Consider a CPU with clock cycle of 10ns that executes program A in 100 clock cycles and access the memory for 50 times during the execution. The CPU uses the cache with miss rate of 7% and Miss Penalty time of 40 ns. Compare the CPU execution time with and without Cache missAssume a 3GHz processor executes three classes of instructions(A, B, C).i. Calculate the average CPI for this sequence of program.ii. Calculate the execution time for this sequence of program.iii. If we use a system with four same processors, there will bespeed up by a factor of 4 for classes A and C, but class B willremain unaffected. Calculate the new execution time for thissystem. What is the overall speed up? Class A B C CPI for class 4 2 10 IC in sequence 100 200 300Q.Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHZ processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is bits per second.