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Find a logic diagram that corresponds to the VHDL structural description in below figure. Note that complemented inputs are not available

Find a logic diagram that corresponds to the VHDL structural description in below figure. Note that complemented inputs are not available

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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Find a logic diagram that corresponds to the VHDL structural description in below figure. Note that complemented inputs are not available
-- Combinational Circuit 1: Structural VHDL Description library ieee, lcdf_vhdl; use ieee.std logic_1164.all, lcdf_vhdl.func_prims.all; entity comb_ckt_1 is port (xl, x2, x3, x4 in std logic; f: out std_logic); end comb_ckt_1; architecture structural_1 of comb_ckt_1 is component NOTI port (inl: in std_logic; out1: out std_logic); end component; component AND2 port (inl, in2 : in std_logic; out1: out std logic); end component; component OR3 port (inl, in2, in3 : in std logic; out1: out sta_logic); end component: signal nl, n2, n3, n4, n5, n6 : std logic; begin g0: NOT1 port map (inl => x1, out1 => n1); gl: NOT1 port map (inl => n3, out1 => n4); g2: AND2 port map (inl => x2, in2 => nl, outl => n2); g3: AND2 port map (inl => x2, in2 => x3, outl => n3); g4: AND2 port map (inl => x3, in2 => x4, outl => n5); g5: AND2 port map (inl => x1, in2 => n4, outl => n6); g6: OR3 port map (inl => n2, in2 => n5, => n6, out1 => f); end structural_1;
Transcribed Image Text:-- Combinational Circuit 1: Structural VHDL Description library ieee, lcdf_vhdl; use ieee.std logic_1164.all, lcdf_vhdl.func_prims.all; entity comb_ckt_1 is port (xl, x2, x3, x4 in std logic; f: out std_logic); end comb_ckt_1; architecture structural_1 of comb_ckt_1 is component NOTI port (inl: in std_logic; out1: out std_logic); end component; component AND2 port (inl, in2 : in std_logic; out1: out std logic); end component; component OR3 port (inl, in2, in3 : in std logic; out1: out sta_logic); end component: signal nl, n2, n3, n4, n5, n6 : std logic; begin g0: NOT1 port map (inl => x1, out1 => n1); gl: NOT1 port map (inl => n3, out1 => n4); g2: AND2 port map (inl => x2, in2 => nl, outl => n2); g3: AND2 port map (inl => x2, in2 => x3, outl => n3); g4: AND2 port map (inl => x3, in2 => x4, outl => n5); g5: AND2 port map (inl => x1, in2 => n4, outl => n6); g6: OR3 port map (inl => n2, in2 => n5, => n6, out1 => f); end structural_1;
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