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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?6. Assume that two numbers: dividend and divisor are saved in memory address M1 and M2 respectively. Quotient and remainder should be saved in R1 and R2 respectively. Write assembly language instructions and then list microoperations for each instruction and list the control signals required to be activated for each microoperation. MBR is used as buffer for any register to register transfer operation. Signal Description: Control signals operation Comments C0 MAR to RAM (through address bus) C1 PC to MBR C2 PC to MAR C3 MBR to PC C4 MBR to IR C5 RAM to MBR C6 MBR to ALU C7 Accumulator to ALU C8 IR to MAR C9 ALU to Accumulator C10 MBR to Accumulator C11 Accumulator to MBR C12 MBR to RAM (through data bus) C13 IR to Control Unit C14 MBR to R1 C15 MBR to R2 C16 MBR to R3 C17 MBR to R4…QUESTION 2 Discuss with examples the main difference between system programming and application programming and explain in your own words how each of these can be carried out in the computer system. With your knowledge in memory addressing modes and using the given opcodes LDA = 00 0000 0000 (00) 0 (x) What will be the content of the address loaded into the accumulator? b. With your knowledge in memory addressing mods and using the given opcodes STCH = OX54 Buffer = 1000 0101 0100 (00) 1 (x) 000 1000 0000 0000 () 011 0000 0000 0000 () What will be target address? Briefly explain the usage of the JSUB and RSUB instruction sets in an SIC architecture coding
- . Consider a system that has multiple processors where eachprocessor has its own cache, but main memory is shared among allprocessors.1. a) Which cache write policy would you use?2. b) The cache coherency problem. With regard to the systemjust described, what problems are caused if a processor has acopy of memory block A in its cache and a second processor,also having a copy of A in its cache, then updates mainmemory block A? Can you think of a way (perhaps morethan one) of preventing this situation, or lessening itseffects?Please help me in these following questions: 1/ A data hazard is when a __________ . a. previous instruction must complete its read or write b. required resource is busy c. branch depends on a previous result d. cache miss occurs 2/ The single-cycle datapath conceptually described in class must have separate instructions and data memories, because a. the formats of data and instructions are different, and hence different memories are needed b. having separate memories is less expensive c. the processor operates in one cycle and can not use a (single ported) memory for two different accesses within that cycle d. None of the above 3/ The ALU does not calculate which of the following statements? a. A selection of which register to read or write from b. An arithmetic result c. A memory address for load/store d. A branch target address 4/ In the CPU datapath multiple signals need to be combined to an output using a __________ . a. register b.multiplexer c. AND gate…Memory address translation is useful only if the total size of virtual memory (summed over all processes) needs to be larger than physical memory. True or False. Justify your answer.
- 10. Q1 : What is an atomic instruction? Show that if the wait operation is not executed atomically, then mutual exclusion may be violated Q2: What is spinlock? Discuss the advantage and disadvantage of using spinlock. Why do you think Solaris, Linux, and Windows 2000 use spinlocks as a synchronization mechanism only on multiprocessor systems and not on single- processor systems?Task#1: Assembly Language Programming: Write down the states of RAM and registers, in line by line Debugging Mode, in the following given scenarios. [org 0x100] mov ax, 3 add ax,1 mov ax,2 mov bx,3 sub bx,ax add ax,bx mov ax,0x4c00 int 0x21 Question find Ax = and Bx = memory address with instructions only 7 min left do fast donot copy from internet there it is wrong else i downoteQ2: CPU Organization Consider the following Accumulator-based CPU instructions: LOAD D ; Acc D (Load ACC with D) MUL E ; Acc Acc * E ADD C ; Acc Acc + C STORE R1 ; R1 Acc (Store Acc to R1) LOAD A ; Acc A SUB B ; Acc Acc-B DIV R1 ; Acc Acc / R1 What is the equation that the above instructions evaluate? Write the equation. Write Stack-based CPU instructions to evaluate that equation. Write General Register-based CPU instructions (two-address instructions) to evaluate the equation.
- a) Suppose two threads T1 and T2 are running concurrently in the same process with a single CPU. Suppose T1 does “Load X into register R1” machine instruction. Then the CPU scheduler switches the CPU to T2. Will T2 see the same vaue of R1 as loaded here by T1? (YES or NO)? Explain in less than 50 words. Be specific. (b) Suppose two threads T1 and T2 are running concurrently in the same process with a single CPU. Is it possible to have a moment (time instant) where both threads have made a request to Memory Unit to read some data (ex. as part of a “Load … into register …” instruction) and Memory Unit has not yet completed either of these two requests? Explain in less than 50 words.Fill-in the correct instruction, assembler directive, or commands. Use small letters only. PROMPT 1.Blank 1 MESSAGE ; Define macro with message as parameter 2. Blank 2 AX ; Store AX register MOV AH, 09H ; Display Message LEA DX, MESSAGE INT 21H POP AX ; restore register 3. Blank 3 ;End of MESSAGE .4.Blank 45.Blank 5 ; Determines that the model (DS and CS) size is 128KB . STACK 200 DATA 6. Blank 6 ; start data segment MES1 DB 10, 13, ‘1. HEX TO BCD $’ MES2 DB 10, 13, ’2. BCD TO HEX $’ MES3 7. Blank 7 10, 13,’3. EXIT $’ ; variable declaration MES4 DB 10, 13, ‘ENTER THE CHOICE: $’ MES5 DB 10, 13, ‘ENTER THE CORRECT CHOICE: $’ MES6 DB 10, 13, ‘$’ MES7 DB 10, 13, ‘ENTER THE FOUR DIGIT HEX NUMBER: $’ MES8…Please help with the following in regards to Nand2Tetris, and hack code, so hack assembly and hack vm. There can be more that one answer to a question if so please explain why. 1a. The A-instruction in the Hack computer performs a. direct addressing. b. immediate addressing. c. indirect addressing. d. bitwise addressing. 1b. Each memory address in the Hack computer references a. a single byte. b. a single word. c. multiple words. d. the D-register 1c. Given the following assembly code: (FOO) @FOO 0;JMP The purpose of the code is to : a. test of the value is = = 0 NO-OP b. jump to address 0 in RAM c. return a 0 to the calling code d. create an endless loop e. end the assembly language program 1d. Given a function called foo() that calls another external function bar() which in turn calls a second function called additup(). Indicate the VM line of code indicating the location in the program that control should be return to: a.@Foo.$bar. b. @Foo$bar$additup.ret.1 c.…