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How many registers would it take to implement the FrameChecker module if the state machine uses binary encoding? module FrameChecker ( input logic clk, input logic Rst, input logic startin, input logic EndIn, output logic Errorout ); typedef enum (sReset, sidle, iActive } StateType; stateType sstate; always @(posedge Clk or posedge Rst) begin if ( Rst) begin Errorout <= 0; sstate <=sReset; end else begin Errorout <= 0; case (sstate) sReset: begin 02 03 04 05 end sstate <= sidle; end sIdle begin if (startIn) begin sstate <= iActive; end end end endmodule iActive: begin if ( EndIn) begin sstate <= sidle; end if ( startIn) begin ErrorOut <= 1; end endcase end Pick one of the choices 00 01

How many registers would it take to implement the FrameChecker module if the state machine uses binary encoding? module FrameChecker ( input logic clk, input logic Rst, input logic startin, input logic EndIn, output logic Errorout ); typedef enum (sReset, sidle, iActive } StateType; stateType sstate; always @(posedge Clk or posedge Rst) begin if ( Rst) begin Errorout <= 0; sstate <=sReset; end else begin Errorout <= 0; case (sstate) sReset: begin 02 03 04 05 end sstate <= sidle; end sIdle begin if (startIn) begin sstate <= iActive; end end end endmodule iActive: begin if ( EndIn) begin sstate <= sidle; end if ( startIn) begin ErrorOut <= 1; end endcase end Pick one of the choices 00 01

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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PLEASE NOTICE THIS SAYS BINARY ENCODING!!!!!!!!!!!!!!!!!!!!!!!

How many registers would it take to implement the FrameChecker module if the state machine uses binary encoding? module FrameChecker ( input logic clk, input logic Rst, input logic startin, input logic EndIn, output logic Errorout ); typedef enum (sReset, sidle, iActive } stateType; StateType sstate; always @(posedge Clk or posedge Rst) begin if ( Rst) begin Errorout <= 0; sstate <= SReset; end else begin Errorout <= 0; case (sstate) SReset end begin sstate <=sIdle; end sIdle: begin if ( startIn) begin sstate <= iActive; end end iActive begin end endmodule if ( EndIn) begin sstate <sIdle; end if ( startIn) begin ErrorOut <= 1; end endcase end Pick one of the choices 00 01 02 0 3 0.4 5
Transcribed Image Text:How many registers would it take to implement the FrameChecker module if the state machine uses binary encoding? module FrameChecker ( input logic clk, input logic Rst, input logic startin, input logic EndIn, output logic Errorout ); typedef enum (sReset, sidle, iActive } stateType; StateType sstate; always @(posedge Clk or posedge Rst) begin if ( Rst) begin Errorout <= 0; sstate <= SReset; end else begin Errorout <= 0; case (sstate) SReset end begin sstate <=sIdle; end sIdle: begin if ( startIn) begin sstate <= iActive; end end iActive begin end endmodule if ( EndIn) begin sstate <sIdle; end if ( startIn) begin ErrorOut <= 1; end endcase end Pick one of the choices 00 01 02 0 3 0.4 5
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