iven a system with a 1 GHz clock (1nsec) and two levels of cache, what is the average ccess time of memory for a single byte? Show your work. takes 4 clocks to access L1 Cache, 10 clocks to access L2 Cache, and 150 clocks to ccess memory. The CHR for L1 Cache is 98%, L2 Cache is 99%, and MHR is 95%.
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- Consider a three-level memory hierarchy, M1, M2 and M3, with access times 1, 10 and 100 clock cycles, costs per byte $0.02, $0.01 and $0.001, and capacities 64K, 512K and 4G Bytes, respectively. (Note that the access times are between the CPU and corresponding memory level). The M1 and M2 hit ratios are 98%, 91%, respectively. What is the AMAT for this system? Round your answer to two decimal places.I have a little bit problem with my late quiz for computer architecture, I get the answer from my lecturer but I still don't feel fully understand, can I ask for some help: In a computer system, the memory has 32 blocks and the cache has 8 blocks. Assume there is only one word per block with 4 bytes in one word. The reference sequence in terms of word location is 0, 2, 4, 10, 5, 12, 8, 18, 13. If the cache is direct-mapped, how many misses do we have if the cache is initially empty? Can you give the hit or miss for each reference?Section 5.5 states that modern server memory modules (DIMMs) employ SEC/DED ECC to protect each 64 bits with 8 parity bits. Compute the cost/ performance ratio of this code to the code from 5.9.1. In this case, cost is the relative number of parity bits needed while performance is the relative number of errors that can be corrected. Which is better?
- A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?A system is using segmentation to map physical memory. Current segment table is as follows. Some of the entries are stored in associative registers as given in second table. Assume that the register access time is 10 nanoseconds and memory access time is (10 x 7) nanoseconds; Find the physical memory address for each of the following logical memory addresses given by <Segment no, offset> Calculate effective memory access time for each (a) <0,3700> (b) <2,3780> (c) <1,200>Consider a two-level memory system (i.e., cache and main memory). Assume the cache access time is 3 clock cycles, and the hit rate is 95%. What should be the main memory access time (penalty) to ensure the memory access efficiency stays at 0.90?
- You are asked to perform capacity planning for a two-level memory system. The first level, M1 is a cache with three capacity choices of 64Kbytes, 128Kbytes, and 256Kbytes. The second level, M2, is a main memory with a 4Mbyte capacity. Let c1 and c2 be the costs per byte and t1 and t2 be the access times for M1 and M2, respectively. Assume c1 = 20 * c2 and t2 = 10 * t1. The cache hit ratios for the 3 capacities are assumed to be 0.7, 0.9 and 0.95, respectively. What is the average memory access time, AMAT, if t1 = 20ns in the three cache designs? (Note that t1 is the time from M1 to CPU and t2 is that from M2 to CPU. This means that t2 includes t1).Suppose that a 32M x 16 main memory is built using 512K × 8 RAM chips and memory is word-addressable. (Please show detailed work) f) If high-order interleaving is used, where would address 32(base 10) be located? (Your answer should be "Bank#, Offset#") g) Repeat (f) for low-order interleaving.Q3 Consider a swapping system in which main memory contains the following hole sizes in memory order: 10K, 4K, 20K, 18K, 7K, 9K, 12K, and 15K. Which hole is taken for successive segment requests of (a) 12K, (b) 10K and (c) 9K for Next-Fit? Assume the last allocated hole is 20K.
- 3- What is the difference between: a- MOV BX,[1234H] and LEA BX,[1234H] b- LDS AX,[200H] and LES AXX,[200H] 4-Use MOV to load address of memory MEM1.Suppose we have a 16-bit main memory address and 32 blocks of cache memory accessible on a byte-addressable computer using 2-way set associative mapping. Display your results after calculating the offset field size based on the fact that each block contains 8 bytes.For a system, RAM = 64KB, Block size = 4 bytes, Cache size = 128 bytes, Direct mapped cache.Calculate the Hit ratio while CPU runs program “Test_Cache”. Also count how many blocks arereplaced in cache memory assuming the cache is empty at the beginning.For the same RAM, block size and Cache memory, what would be the Hit ration in case of FullyAssociative Mapping?For the same RAM, block size and Cache memory, what would be the Hit ration in case of 4-way SetAssociative Mapping?Main Program—“Test_Cache”