Minimize the following Boolean function use five variables K-map 1. In SOP and draw the logic circuit (Sum Of Product) 2. In POS and draw the logic circuit (Product Of Sum) F(A, B, C, D, E) = [IM(0,2,6,10,13,14,16,19,25,30) + d(1,4,5,11,21,22,24,27,31)
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- Design a gating circuit which lights up a bulb, when its 4-bit binary number inputs detected the presence of a number divisible by 2.a. Show the truth table for this logic circuitb. State and simplify the Boolean expression using Karnaugh Mapc. Draw the logic circuit.a) Kindly design a Master-slave J-K flip-flop using NAND gates only and state race-around condition, and how it can be eliminated in a Master-slave J-K flipflop? A multiplexer (MUX) also known as data selector, is a logic circuit which allows the digital information from multi-inputs to a single output line(b) Design a 8 to 1 multiplexer by using the four variable function given by F (A, B, C, D) = ∑m = (013489 15) (c) OUR school AIT has lockers in all the campus that she often rent them out to students who needs them, upon graduation they are taken back by the school authorities. Kindly express the process of opening this locker in terms of digital operation.Determine the simplified output expression of the logic diagram using appropriate K map. F(A, B, C, D, E) =m(0, 5, 7, 9, 11, 13, 15, 18, 19, 22, 23,25, 27, 28, 29, 31)
- KINDLY ANSWER. THANKS Derive the Boolean expressions of one-bit comparator and two-bit comparators. How do you realize a higher magnitude comparator using lower bit comparator? Design a 2-bit comparator using a single Logic gate? Design an 8-bit comparator using two numbers of IC 7485?Given a sequential logic circuit expression asX(t+1) = p'X+pYY(t+1) = pX'+p'Ywhere X and Y are the two flip-flop outputs and p is the main external input.Draw the state transition table for the above-given logic function.Also, draw the state transition diagram associated with it.And What is the behavior of the circuit?We wish to design a digital system with two flip-flops, say B and C, and one 4-bit binarycounter A, in which the individual flip-flops are denoted by A4, A3, A2, A1. A start signal Sinitiates the system operation by clearing the counter A and flip-flop C, and settling flip-flop B toone. The counter is then incremented by one starting from the next clock pulse and continues toincrement until the operations stop. Counter bits A3 and A4 determine the sequence ofoperations:If A3 = 0, B is cleared to 0 and the count continues.If A3 = 1, B is set to 1; then if A4 = 0, the count continues, but if A4= 1, C is set to 1 on the nextclock pulse and the system stops counting.Then if S = 0, the system remains in the initial state, but if S = 1, the operation cycle repeats.(a) Draw the ASM Chart(b) Draw the equivalent one flip-flop per state
- 1-Using the Karnaugh Method, design and draw the circuit of the logic circuit that gives the result of the multiplication of the two-bit numbers "AB" and "CD" according to minterms (SOP). Do not make any further simplifications before or after the Karnaugh Method. In tables and Karnaugh, ensure that the least significant bit is on the far right and the entries are sorted alphabetically. Make sure that the circuit you have drawn is understandable, the function you have written and the truth table are readable.Derive the Boolean expression for the logic circuit shown below in the minimum SOP pls show workA circuit which takes a binary-coded decimal (BCD) number as input s to be designed such that the single output Q is true if the input is a prime number (remerber that 0 and 1 count as prime numbers). (a)Draw a truth table that specifies the above circuit (b)Using the truth table you have constructed and the Karnaugh map method find the minimised Boolean expression for the output Q. (c)Implement the digital circuit using the minimum number of 2-input logic AND, OR gates and inverters (NOT.
- 4.1 Investigate if the following Boolean “identity” is correct, or not. If it is not correct, formulate the correct version of the identity (?′?+?)′=?+?′?′. [2]4.2 Use the identities of Boolean algebra to verify the following identity: [4]?(?+?)+??′+??′+?=?+?+?4.3 Consider the logic gate circuit below:a) Formulate the Boolean expression corresponding to the output of the logic circuit diagram above. [2]b) Hence, show that the Boolean expression formulated in part (a) reduces to ??+?. [3]c) Draw the logic gate circuit diagram corresponding to the reduced expression inpart (b) above. 3.1 Let r, s, t denote the statements “Joe is registered for MCI511S”, “Joe will go to the zoo next week”, “Joe is registered for PBT512S”, respectively. Translate the symbolic statement (∼?∨?)→∼? into words. [2]3.2 Write the negation of the statement “If Joe writes the exam, he will go the airport but he will not catch the flight”. [2]3.3 Determine the truth value of the compound statement (?∧∼?)∨∼?, if p…Kindly design a Master-slave J-K flip-flop using NAND gates only and staterace-around condition, and how it can be eliminated in a Master-slave J-K flipflop? A multiplexer (MUX) also known as data selector, is a logic circuit which allowsthe digital information from multi-inputs to a single output lineBoolean expression of a logic operation is given below: (a) Simplify the Boolean expression using Boolean algebra and De Morgan’s Theorems (b) Draw the circuit to implement the expression you obtain using NAND or NOR gates on