Determine the number of bits for each cache for the , , and address bits cache size block size cache architecture tag index block offset 32 32 KB 16 B direct mapped 48 64 KB 8 B 2-way set associative 40 128 KB 32 В 4-way set associative

Consider a 2-way set associative cache (S,E,B,m) = (8,2,4,13) Excluding the overhead of the tags and valid bits, what is the capacity of this cache? Draw a figure of this cache. Draw a diagram that shows the parts of the address that are used to determine the cache tag, cache set index, and cache block offset.

Calculate the number of bits used for data and overhead for the following caches A. 64-block/line, direct-mapped, write-through, 8 byte block/line

Assume the address format for a fully-associative cache is as follows: 6 bits 2 bits Tag Offset 8 bits Given the cache directory is as shown in the diagram below, indicate whether the memory reference Ox5E results in a cache hits or a miss. Tag valid Block 000 110110 001 000001 010 000010 011 000101 100 001000 1 101 100010 110 010111 111 110110 O Hit O Miss

Explain the differences between a directly mapped cache and a fully associative cache.

A cache is organized as a 4 way set associative cache Each set's cache line consists of 4 words (meaning there are 16 bytes per line, for each set of the cache). Each set individually has one Valid bit, and one Dirty bit, for each line. The tag field of this cache is 8 bits wide. The address is 32 bits wide. Question 1a) What is the number of cache lines? Question 1b) What is the total number of 'memory bitcells' that are needed to design this cache (note, this includes the bitcells required for the tags, valid and dirty bits).

Distinguish between an associative and a direct-mapped cache.

Explain why it is difficult to devise a suitable cache replacement technique for all address sequences.

What are the miss rates for 64 KiB data caches with varied set associativity, broken down by miss type (cold, capacity, and conflict misses) for each benchmark?

Consider a cache with 32KİB data, 16-word blocks, and 24-bit addresses, answer the following questions: a) For the direct-mapped configuration, determine the number of index bits and tag bits in the 24-bit address. b) For 4-way set associative configuration, determine the number of index bits and tag bits in the 24-bit address. c) For fully associative contiguration, determine the number of index bits and tag bits in the 24-bit address. d) For an 8-way set associative configuration, identify the set number in the cache to which the following 24-bit memory address maps: Ox001Z00 (Hexadecimal notation) where Z is the least significant digit in your student ID (written as a decimal number)