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Question 35 A processor running a program makes 100 accesses to memory addresses. 80% are to L1 only, 10% are to L2 and L1, and 10% are to memory, L2, and L1. What is the total number of cycles? Assume cycles simply add, so the 1 access that involves memory takes 10 + 2 +1= 13 cycles. %3D Processor L1 cache L2 cache Memory Drive 32 KB 1 cydle 1 MB 2 cycles SRAM SRAM 4 GB 10 cycles DRAM Cachememoryldrive not drawn o scale. Listed sizes and access cycles are just examples 1 TB 100 cycles Non-volaile Flashidak O 80 130 O 240 110

Question 35 A processor running a program makes 100 accesses to memory addresses. 80% are to L1 only, 10% are to L2 and L1, and 10% are to memory, L2, and L1. What is the total number of cycles? Assume cycles simply add, so the 1 access that involves memory takes 10 + 2 +1= 13 cycles. %3D Processor L1 cache L2 cache Memory Drive 32 KB 1 cydle 1 MB 2 cycles SRAM SRAM 4 GB 10 cycles DRAM Cachememoryldrive not drawn o scale. Listed sizes and access cycles are just examples 1 TB 100 cycles Non-volaile Flashidak O 80 130 O 240 110

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question 35 A processor running a program makes 100 accesses to memory addresses. 80% are to L1 only, 10% are to L2 and L1, and 10% are to memory, L2, and L1. What is the total number of cycles? Assume cycles simply add, so the 1 access that involves memory takes 10 + 2 +1= 13 cycles. %3D Processor L1 cache L2 cache Memory Drive 32 KB 1 cycle 1 MB 2 cycles SRAM SRAM 4 GB 10 cycles DRAM Coche/memorydrive not drawn to scale. Listed sizes and access cycles are just examples 1 TB 100 cycles Non-volatile Fiashidak O 80 O 130 240 O 110
Transcribed Image Text:Question 35 A processor running a program makes 100 accesses to memory addresses. 80% are to L1 only, 10% are to L2 and L1, and 10% are to memory, L2, and L1. What is the total number of cycles? Assume cycles simply add, so the 1 access that involves memory takes 10 + 2 +1= 13 cycles. %3D Processor L1 cache L2 cache Memory Drive 32 KB 1 cycle 1 MB 2 cycles SRAM SRAM 4 GB 10 cycles DRAM Coche/memorydrive not drawn to scale. Listed sizes and access cycles are just examples 1 TB 100 cycles Non-volatile Fiashidak O 80 O 130 240 O 110
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