Using the following graphic find the answer to the following questions: A byte-addressable computer has a smal data cache capable of holding eight 32-bit words. Each cache line consists of two 32-bit word. When a given program is executed, the processor reads data sequentially from the following hexadecimal addresses: s00,514,328,33C,2F0,200,324,518,33C444,4F4 The pattern is repeated 2 times. The cache is initiall empty. Show the contents of the cache at the end of each pass through the loop if a direct-mapping cache is used and compute the hit rate. What is the Hit Ratio? What is the Miss Ratio? How many attempts were there?

Using the following graphic find the answer to the following questions: A byte-addressable computer has a smal data cache capable of holding eight 32-bit words. Each cache line consists of two 32-bit word. When a given program is executed, the processor reads data sequentially from the following hexadecimal addresses: s00,514,328,33C,2F0,200,324,518,33C444,4F4 The pattern is repeated 2 times. The cache is initiall empty. Show the contents of the cache at the end of each pass through the loop if a direct-mapping cache is used and compute the hit rate. What is the Hit Ratio? What is the Miss Ratio? How many attempts were there?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

See similar textbooks

Similar questions

Assume we have a computer with 512 blocks of cache memory with a total capacity of 128K bits. Answer the following questions knowing that the computer operates in a word addressable mode and that the format of the memory address as perceived by the Fully associative cache scheme is as shown below: Cache Format with Full Associativity 19 5 1- How many words are in each cache block? 2- How big are the letters in each word? 3- How large is the primary memory? 4- What is the total number of blocks in main memory? 5- Draw the memory address format as observed by the Direct Mapped Cache technique, including the fields and their sizes.
Assume that we have a computer with a cache memory of 512blocks with a total size of 128K bits. Knowing that the computer uses a word addressable mode and the format of the memory address as seen by the Fully associative cache scheme is as shown below, answer the below questions: Fully Associative Cache Format 1- How many words do we have in each cache block? 2- What is the size of each word? 3- What is the size of the main memory? 4- How many blocks are there in the main memory? 5- Draw the format of the memory address as seen by the Direct Mapped Cache scheme, showing the fields as well as their sizes.
Assume that we have a computer with a cache memory of 512 blocks with a total size of 128K bits. Knowing that the computer uses a word addressable mode and the format of the memory address as seen by the Fully associative cache scheme is as shown below, answer the below questions: Fully Associative Cache Format 19 5 1- How many words do we have in each cache block? 2- What is the size of each word? 3- What is the size of the main memory? 4- How many blocks are there in the main memory? 5- Draw the format of the memory address as seen by the Direct Mapped Cache scheme, showing the fields as well as their sizes.
Computer Science Consider a direct-mapped cache with 8 lines, each holding 16 bytes of data. The cache is byte-addressable and the main memory consists of 64 KB, which is also byte-addressable. Assume that a program reads 16KB of memory sequentially. Answer the following questions:a) How many bits are required for the tag, index, and offset fields of a cache address?b) What is the cache size in bytes?c) What is the block size in bytes?d) What is the total number of blocks in main memory?e) How many cache hits and misses will occur for the program, assuming that the cache is initially empty?f) What is the hit ratio?g) Give an example virtual address (in BINARY) that will be placed in cache line 5.
Assume that we are having a computer with the following characteristics: 1MB of main memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 KB. For the main memory addresses of FF010, the corresponding set number for a four-way set associative cache will be?
Suppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 12 bits wide.The cache is two-way set associative (E = 2), with a 4-byte blocksize (B = 4) and four sets (S = 4).
Suppose a byte-addressable computer using set associative cache has 4Mbyes of main memory and a cache of 64 blocks, where each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache? Show all work and explain how you got the answers please. Thanks
A computer of 32 bits has a cache memory of 64 KB with a cache line size of 64 bytes. The cache access time is 20 ns, and the miss penalty is 120 ns. The cache is 2-way associative. a) What is the number of cache lines? b) What is the number of cache sets? c) What is the number of lines per set? d) Draw a scheme of this cache. e) Calculate the time to read a word in case of miss.
Suppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cache
Memory Hierarchy and Cache Suppose that we have a computer that uses a memory address of 12-bits. This computer has a 64-byte cache with 16 bytes per frame. The computer accesses a number of memory locations throughout the course of a running program. Suppose this computer uses direct-mapped cache. The system accesses the following memory addresses (given in hex) in this exact order: F2E, A17, 2E0, 44E, 34F, 341, B50, B58 a. What is the hit ratio for the memory reference sequence given above? b. Show the content of each cache frame following each memory reference (frame content to be shown as tag +frame index) c.If we keep the same cache size and the same frame size but switch to a 2-way set associative cache mapping scheme. Given the memory address reference 555, indicate where we would look in the cache to find this data. Indicate which fields will be used to find the exact location?
Suppose memory access takes 100 ns and register access takes 1 ns (or less), calculate and compare the computational speed of the three code snippets. Assume CPU instructions such as XOR, ADD, also take 1 ns and we flush everything in the cache before executing the programs. Program snippet 1: Mov EAX, [0x 8002 B001] Mov EBX, EAX XOR EAX, EAX Program snippet 2: Mov ECX, 0 Mov EAX, 1 ADD ECX, EAX Mov [0x 8009 0001], ECX Mov EAX, [0x 8009 0010] Program snippet 3: Mov EAX, Ox 4001 0000 Mov EBX, Ox 4001 0001 ADD EAX, EBX XOR EBX, EBX
Suppose a computer using set associative cache has 221 words of main memory and a cache of 64 blocks, where each cache block contains 4 words. a)If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and word fields? b)If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?