For a system, RAM - 64KB, Block size - 4 bytes, Cache size - 128 bytes, Direct mapped cache. Function NSU-1Calculate the Hit ratio while CPU runs program "Test_Cache". Also count how many blocks arereplaced in cache memory assuming the cache is empty at the beginning.For the same RAM, block size and Cache memory, what would be the Hit ration in case of FullyAssociative Mapping?For the same RAM, block size and Cache memory, what would be the Hit ration in case of 4-way SetAssociative Mapping?Main Program"Test_Cache"Memory address (decimal)6.Memory address (decimal)0136Instruction-10137Instruction-20138Instruction-30139Instruction-4 (return to Instruction-8 of mainprogram -. Test_Cache)Function NSU-2Memory addresN (decimal)0003Instruction-10004Instruction-20128Instruction-10005Instruction-3 (Call Function NSU-2)0129Instruction-20006Instruction-40130Instruction-30007Instruction-7 (Call Function NSU-1)0131Instruction-40008Instruction-80132Instruction-50009Instruction-9 (End of program)0133Instruction-6 (return to Instruction-4 of mainprogram- Test Cache)

Name: For a system, RAM - 64KB, Block size - 4 bytes, Cache size - 128 byte
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Description: For a system, RAM - 64KB, Block size - 4 bytes, Cache size - 128 bytes, Direct mapped cache. Function NSU-1Calculate the Hit ratio while CPU runs program "Test_Cache". Also count how many blocks arereplaced in cache memory assuming the cache is empt

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For a system, RAM - 64KB, Block size - 4 bytes, Cache size - 128 bytes, Direct mapped cache. Function NSU-1 Calculate the Hit ratio while CPU runs program "Test_Cache". Also count how many blocks are replaced in cache memory assuming the cache is empty at the beginning. For the same RAM, block size and Cache memory, what would be the Hit ration in case of Fully Memory addres (decimal) 0136 Instruction-1 0137 Instruction-2 Associative Mapping? For the same RAM, block size and Cache memory, what would be the Hit ration in case of 4-way Set Associative Mapping? Main Program"Test Cache" Memory address (decimal) 0138 Instruction-3 0139 Instruction-4 (return to Instruction-8 of main program Test_Cache) -. Function NSU-2 0003 Instruction-1 Memory address (decimal) 0004 Instruction-2 0128 Instruction-1 Instruction-3 (Call Function NSU-2) 0129 O130 0005 Instruction-2 0006 Instruction-4 Instruction-3 0007 Instruction-7 (Call Function NSU-1) 0131 Instruction-4 0008 Instruction-8 0132 Instruction-5 0009 Instruction-9 (End of program) 0133 Instruction-6 (return to Instruction-4 of main program- Test Cache)

For a system, RAM - 64KB, Block size - 4 bytes, Cache size - 128 bytes, Direct mapped cache. Function NSU-1 Calculate the Hit ratio while CPU runs program "Test_Cache". Also count how many blocks are replaced in cache memory assuming the cache is empty at the beginning. For the same RAM, block size and Cache memory, what would be the Hit ration in case of Fully Memory addres (decimal) 0136 Instruction-1 0137 Instruction-2 Associative Mapping? For the same RAM, block size and Cache memory, what would be the Hit ration in case of 4-way Set Associative Mapping? Main Program"Test Cache" Memory address (decimal) 0138 Instruction-3 0139 Instruction-4 (return to Instruction-8 of main program Test_Cache) -. Function NSU-2 0003 Instruction-1 Memory address (decimal) 0004 Instruction-2 0128 Instruction-1 Instruction-3 (Call Function NSU-2) 0129 O130 0005 Instruction-2 0006 Instruction-4 Instruction-3 0007 Instruction-7 (Call Function NSU-1) 0131 Instruction-4 0008 Instruction-8 0132 Instruction-5 0009 Instruction-9 (End of program) 0133 Instruction-6 (return to Instruction-4 of main program- Test Cache)

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Take into account the following scenario: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Since there are 8 bytes in a block, you can use that information to calculate how big the offset field has to be.
Recall that we have two write policies and write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches: L1 L2 Write through, non-write allocate Write back, write allocate 1. Buff ers are employed between diff erent levels of memory hierarchy to reduce access latency. For this given confi guration, list the possible buff ers needed between L1 and L2 caches, as well as L2 cache and memory.2. Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.3. For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches), confi guration, describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.Consider the following program and cache behaviors. Data Reads per1000 Instructions Data Writes per1000 Instructions Instruction…
Suppose a computer using direct-mapped cache has 232 (that's 232)232) bytes of byte-addressable main memory, and a cache size of 512 bytes, and each cache block contains 64 bytes. How many blocks of main memory are there? What is the format of a memory address as seen by cache, i.e. what are the sizes of the tag, block, and offset fields? To which cache block will the memory address 0x13A4498A map?
Q.Assuming a 2-way set-associative cache What is the hit ratio for this cache on the given sequence of memory accesses?
Here is the question: A direct-mapped cache consists of 8 blocks. A byte-addressable main memory contains 4K blocks of eight bytes each. Access time for the cache is 20 ns and the time required to fill a cache slot from main memory is 300 ns. Assume a request is always started in sequential to cache and then to main memory. If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty. b) Compute the hit ratio for a program that loops 3 times from address 0 to 75 (base 10) in memory. For b, another example has been provided in regards to a previous problem: A direct-mapped cache consists of eight blocks. Main memory contains 4K blocks of eight words each. Access time for the cache is 22 ns and the time required to fill a cache slot from main memory is 300ns (this time will allow us to determine the block is missing and bring it into cache). Assume a request is always started in parallel to both cache and to…
Consider a small 2-way set associative cache memory, consisting of 4 blocks. For choosing the block to be replaced, use LRU scheme. Consider that block address 4 and 2 are already there in cache. The number of cache misses for the following sequence of block addresses 4, 6, 8, 16, 2, 2, 4 are?
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A Direct mapped cache has a capacity of 16-word cache and a block size of 4 words. Consider the following repeating sequence of lw addresses (given in hexadecimal): 74 A0 78 38C AC 84 88 8C 7C 34 38 13C 388 18C Determine the effective miss rate if the sequence is input to the following caches, ignoring startup effects.
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Question 1 Consider the size of main memory as 32 Bytes and the size of cache memory as 8 Bytes. Implement the Set-Associative mapping technique. Do the following: a) Find the number of bits to address 32 bytes in main memory b) Write the formula to map block of main memory to set of cache memory c) Find the block size, line size, set size, tag size d) Draw the figure to show the distribution of main memory in desired blocks containing bytes e) Draw the figure to show the distribution of cache memory in desired lines containing tag numbers, respective blocks, and byte numbers f) Show the tag allocation for each set (and line) of cache memory
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