3. Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate in Figure 1 (the gate that goes to the SR latch) to the input of the lower gate (instead of the inverter output).
3. Use four NAND gates only (without an inverter). This can be done by connecting the output of the upper gate in Figure 1 (the gate that goes to the SR latch) to the input of the lower gate (instead of the inverter output).
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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