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- 1:The output of a logic gate is 1 when all the input are at logic 1 and a . OR and EX - NOR Gate b . AND Gate and EX - OR Gate C. OR and EX - OR Gate d . NAND and OR Gate 2: Choose an application of A / D convertor a. Sonar systems b. Radars and Jammers C. Digital Audio apllications d. Encoders 3: Find the simplification of AB + B ( B + C ) + C ( B + C ) a. C + A b. B + C c. 1 d. A + 4: Choose a correct number of input lines for a decoder which has 128 output lines a . 14 b . 7 c . 1 d . 128 6: Select a suitable example for sequential logic circuit . a . Encoder b . None of the given choices c . Counters d . PALA circuit which takes a binary-coded decimal (BCD) number as input s to be designed such that the single output Q is true if the input is a prime number (remerber that 0 and 1 count as prime numbers). (a)Draw a truth table that specifies the above circuit (b)Using the truth table you have constructed and the Karnaugh map method find the minimised Boolean expression for the output Q. (c)Implement the digital circuit using the minimum number of 2-input logic AND, OR gates and inverters (NOT.Simplify the following Boolean expression after that you will have to draw a logic circuit for the simplified function using only 7 NOR gates: F(K,L,M, N) = Σ (0,3,4,8,11,13) + Σ d(5,9,12,15) Suppose you want to send a BCD number "(100100110101)BCD" to your friend and the sending device has an odd parity bit generator that can process a single BCD digit. Design an odd parity bit generator to send BCD digit and find out parity bit for given number.
- 1-Using the Karnaugh Method, design and draw the circuit of the logic circuit that gives the result of the multiplication of the two-bit numbers "AB" and "CD" according to minterms (SOP). Do not make any further simplifications before or after the Karnaugh Method. In tables and Karnaugh, ensure that the least significant bit is on the far right and the entries are sorted alphabetically. Make sure that the circuit you have drawn is understandable, the function you have written and the truth table are readable.NAND gates require one less transistor thanAND gates. They are often used exclusively toconstruct logic circuits. One such logic circuit that usesthree-input NAND gates is shown in Figure P12.25.a. Determine the truth table for this circuit.b. Give the logic equation that represents the circuit(you do not need to reduce it).1. Floating Point Numbersa. Show the difference between IEEE 16, 32, 64, 128-bit floating-point numbers.b. Express the following numbers in hexadecimal IEEE 32-bit floating-pointformat. i. 320ii. -622. Design a circuit that implements function p below using AND, OR, and NOT gates.DO NOT change the form of the equation. ?(?0, ?1, ?2, ) = {?2(?0?1 + ?̅0?̅1)}. (?̅2 + ?̅1)4. Show how the unsigned serial multiplication method would compute M × Q where M = 10110and Q = 01101. M and Q are unsigned numbers. For each step, describe in words what is happening (shift left, shift right, add/subtract M or Q into product, set a bit, etc.), and showthe product (or partial product) for that step. (Note: Q is the multiplier and M is themultiplicand.)
- Solve these three MCQs. No need to explain the MCQs. Reference book Barry B Brey 8th edition. 1) During the DMA bus cycle the system bus is driven by the DMA controller, not by the MPUSingle choice. a) No b) Yes 2) There are _______ banks of data memory in 16F877.Single choice. a) 3 b) 4 c) 6 d) 2 3)There are total of ___________ instructions in PIC 16F877.Single choice. a) 39 b) 31 c) 43 d) 35Design a 4-bit arithmetic circuit, with two selection variables S1 and S0, that generates the arithmetic operations in the following table. Draw the logic diagram for a single bit stage. Note that B’ represents “Not B”. Draw the logic diagram for a single bit stagKINDLY ANSWER. THANKS Derive the Boolean expressions of one-bit comparator and two-bit comparators. How do you realize a higher magnitude comparator using lower bit comparator? Design a 2-bit comparator using a single Logic gate? Design an 8-bit comparator using two numbers of IC 7485?
- For Q(a,b,c)= ∏M(0,2,4,6) what is the reduced form of the logic function in POS form? A) (B’+C’) .(B+C’) B) B’C’+BC’ C) C D) C'I was able to fill out the truth table for part A. I ONLY need help for PART B. B) Implement the logic function (z) using the multiplexer 74HC151 shows in the picture.Q (A, B, C) = A̅ .B̅. C +A̅ .B. C + A .B. C̅ + A.B.C Karnaugh function given in the form Using the mapping method, you can use the simplified function separately in terms of minterms and maxterms. obtain. Output functions with AND NOT for minterms and OR for maxters. Install separately with logic doors.