The following equation was suggested both for cache memory and disk cache memory Ts = Tc + M * Tp %3D Generally this equation to a memory hierarch' with N levels instead of just two levels.
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A: The Answer is
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- Suppose that 16M × 16 memory built using 512K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved? 3. c) How many address bits are needed for each RAM chip?4. d) How many banks will this memory have?5. e) How many address bits are needed for all memory?6. f) If high-order interleaving is used, where would address 14 (which is E in hex) be located?7. g) Repeat exercise 9f for low-order interleaving.Memory address translation is useful only if the total size of virtual memory (summed over all processes) needs to be larger than physical memory. True or False. Justify your answer.Please calculate the total clock cycles for each functionseperately then calculate how much faster would the functions be if a better data cache reduced the average memory operations time to 4 cycles? Code: # Calculating Fibonacci numbers# fib(0) = 0# fib(1) = 1# fib(n) = fib(n-1)+fib(n-2).text.globl mainprint_str:li $v0, 4 # print string at ($a0)syscall #jr $ra # return; print_eol:la $a0, eol # print "\n"li $v0, 4 #syscall #jr $ra # return; print_int:li $v0, 1 # print integer ($a0)syscall #jr $ra # return; # fib(n) - recursive function to compute nth Fibonacci number#fib: sub $sp,$sp,12 # save registers on stacksw $a0, 0($sp) # save $a0 = nsw $s0, 4($sp) # save $s0sw $ra, 8($sp) # save $ra to allow recursive calls bgt $a0,1, gen # if n>1 then goto generic casemove $v0,$a0 # output = input if n=0 or n=1j rreg # goto restore registers gen: sub $a0,$a0,1 # param = n-1jal fib # compute fib(n-1)move $s0,$v0 # save fib(n-1) sub $a0,$a0,1 # set param to n-2jal fib # and make recursive…
- Explain why various memory management techniques, such as base/bounds and paging, have difficulty with asynchronous I/O operations.Because volatile RAM (Random Access Memory) already exists, what's the point of using a slower, less reliable cache memory instead?The electrical components called transistors are used in both random access memory (RAM) and cache memory. To what extent, if at all, can a computer get by with using just one kind of memory to carry out all of its functions?What is the point of using cache memory if we already have volatile RAM (Random Access Memory)?Transistors are used in both random-access memory (RAM) and cache memory. Is it conceivable, if at all possible, to employ just one kind of memory to carry out all of a computer's functions?
- Suppose that a 32M X 32 memory built using 512K X 8 RAM chips and memory is word-addressable. 1) How many RAM chips are necessary? 2) If we were accessing one full word, how many chips would be involved? 3) How many address bits are needed for each RAM chip? 4) How many banks will this memory have? 5f) If high-order interleaving is used, where would address 0x11011 be located? (Answer should be: bank# & offset#)Assume a cache memory hit ratio is 93% and the hit time is one cycle, but the miss penalty is 40 cycles. Then, Compute the average memory access time (AMAT)Suppose that a 64M x 16 main memory is built using 512K × 8 RAM chips and memory is word-addressable. a) How many RAM chips are necessary?b) If we were accessing one full word, how many chips would be involved?c) How many address bits are needed for each RAM chip?d) How many banks will this memory have?e) How many address bits are needed for all of memory?f) If high-order interleaving is used, where would address 32(base 10) be located? (Your answer should be "Bank#, Offset#")g) Repeat (f) for low-order interleaving.
- Cache memory seems unnecessary if RAM and cache memory both use transistors for storage. Can one single memory type be used for everything?You play the role of the instructor of CPSC440. Your CPSC440 students need more practice on the cache memory concept. You, as a professor of the CPSC440 course, decide to solve one more cache memory access problem (in addition to two problems in our Assignment). The new problem is: You are given a direct-mapped cache of 4 blocks with four-word per block (a total of 16 words in the cache). The main memory size is 64 words. We have the following memory access sequence: Word1, Word 8, Word0, Word 17, Word 14, Word 62, Word 55, Word 25, Word 16, and Word 15. You need to write an essay that explains how you solve this problem. You also need to show your students the final cache content using the given table shown below.You also need to explain to your students the result of hit or miss for each word access.A computer is using a fully associative cache and has 216 bytes of main memory (byte addressable) and a cache of 64 blocks, where each block contains 32 bytes. a. How many blocks of main memory are there? b. What will be the sizes of the tag, index, and byte offset fields? c. To which cache set will the memory address 0xF8C9(hexadecimal) map?