1. The hypothetical machine of figure 3.4 also has two I/O instructions: 0011= Load AC fro I/O 0111= Store AC to I/O In these cases the 12-bit address identifies a particular I/O device. Show the program execution (using format of figure 3.5) for the following program: 1. Load AC from device 5. 2. Add contents of memory location 940. 3. Store AC to device 6. Assume that the next value received from device 5 is 3 and that location 940 contains value of 2.

1. The hypothetical machine of figure 3.4 also has two I/O instructions: 0011= Load AC fro I/O 0111= Store AC to I/O In these cases the 12-bit address identifies a particular I/O device. Show the program execution (using format of figure 3.5) for the following program: 1. Load AC from device 5. 2. Add contents of memory location 940. 3. Store AC to device 6. Assume that the next value received from device 5 is 3 and that location 940 contains value of 2.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
QUESTION ONE (1) 1. The hypothetical machine has two I/O instructions: 0011 = Load AC from I/O 0111 = Store AC to I/O In these cases, the 12-bit address identifies a particular I/O device. List the steps for every execution for the following program and illustrate using table that explain the process below : a. Load AC from device 5. b. Add contents of memory location 940. c. Store AC to device 6. d. Assume that the next value retrieved from device 5 is 3 and that location 940 contains a value of 2.
1. The hypothetical machine has two I/O instructions: 0011 = Load AC from I/O 0111 = Store AC to I/O In these cases, the 12-bit address identifies a particular I/O device. List the steps for every execution for the following program and illustrate using table that explain the process below : a. Load AC from device 5. b. Add contents of memory location 940. c. Store AC to device 6. d. Assume that the next value retrieved from device 5 is 3 and that location 940 contains a value of 2. Please pointing a, b,c ans. Because one I already upload this question and I didn't understand which one is and of a...please write ans a, b , c please
1) If CS = 25H then find the second and second to last physical address of this segment.2) Suppose you want to design a Microwave and are in need of a processing unit. Would you choose to use a microprocessor or a microcontroller for this purpose? Explain with logic. 3) “The data bus is bidirectional but the address bus is unidirectional”Give your opinion on this statement.
1. The hypothetical machine of Figure 3.4 also has two I/O instructions: In these cases, the 12-bit address identifies a particular I/O device. Show the program execution (using the format of Figure 3.5) for the following program: 2.Add contents of memory location 940.
Suppose that a 64M x 16 main memory is built using 512K × 8 RAM chips and memory is word-addressable. a) How many RAM chips are necessary?b) If we were accessing one full word, how many chips would be involved?c) How many address bits are needed for each RAM chip?d) How many banks will this memory have?e) How many address bits are needed for all of memory?f) If high-order interleaving is used, where would address 32(base 10) be located? (Your answer should be "Bank#, Offset#")g) Repeat (f) for low-order interleaving.
Suppose that a 2M × 16 main memory is built using 256K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved? 3. c) How many address bits are needed for each RAM chip?4. d) How many banks will this memory have?5. e) How many address bits are needed for all memory?6. f) If high-order interleaving is used, where would address 14 (which is E in hex) be located?7. g) Repeat exercise 9f for low-order interleaving.
1. Name all of the general purpose registers and some of their special functions. 2. How are the segment registers used to form a 20-bit address? 3. (a) If CS contains 03E0H and IP contains 1F20H, from what address is the next instruction fetched? (b) If SS contains 0400H and SP contains 3FFEH, where is the top of the stack located? (c) If a data segment deigns at address 24000H, what is the address of the last location in the segment? 4. Explain what the instruction array and data caches are used for. 5. What is the EU and BIU, and what purpose in the microcomputer? 6. Two memory locations, beginning at address 3000H, contain the bytes 34H and 12H. What is the word stored at location 3000H? See Figure 2.26 for details. Address 3000 Data 34 3001 12 Figure 2.26 For question 6 7. What is a physical address? What are the differences between the 8086 logical and physical memory maps? 8. May memory segments overlap? If so, what is the minimum number of overlapped bytes…
Suppose that 16M × 16 memory built using 512K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved? 3. c) How many address bits are needed for each RAM chip?4. d) How many banks will this memory have?5. e) How many address bits are needed for all memory?6. f) If high-order interleaving is used, where would address 14 (which is E in hex) be located?7. g) Repeat exercise 9f for low-order interleaving.
Consider the following store instruction: SW R1, 0x000F(R0). Assume that the registers R0 and R1 are initialized with 0x00000001 and 0x53A78BC Frespectively. A section of the MIPS byte addressable data memory is shown. Give the memory word of the following memory locations after the SW operation: (a). 0x00000015. (b). 0x00000014. (c). 0x00000013. (d) 0x00000012.(e). 0x00000011. (f). 0x00000010.
Suppose that a 32M X 32 memory built using 512K X 8 RAM chips and memory is word-addressable. 1) How many RAM chips are necessary? 2) If we were accessing one full word, how many chips would be involved? 3) How many address bits are needed for each RAM chip? 4) How many banks will this memory have? 5f) If high-order interleaving is used, where would address 0x11011 be located? (Answer should be: bank# & offset#)
Assume that the microprocessor can directly address 1M with a and 8 data pins. The maximum RAM system can design by using the following RAM chips is. Size of RAM chip Number of Chips 2K × 4 6 4K × 4 7 1k × 4 512 × 8 5 10 a. 27k × 8 b. 26k × 8 c. None of them d. 24k × 8 e. 25k × 8