2. Consider the following circuit: where Clk is the clock signal. В D Q D Clk- Figure 1. Logic circuit for problem 2 (a) What is the activity factor of signal A? (b) What is the activity factor of signal B?
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- Flip-flops Give the disadvantages and advantages of Positive Edge Triggering vs Negative Edge Trigerring. Then, give an example of digital circuit and explain where a) Positive Edge is used and b) Negative edge is used(a) Draw a NAND logic diagram that implements the complement of the following function: F (A, B, C, D)=Σ(0, 1, 2, 3, 6, 10, 11, 14), and (b) repeat for a NOR logic diagram.A certain packaged IC chip can dissipate 5W. Supposewe have a CMOSIC design that must fit on onechip and requires 10 million logic gates. What is theaverage power that can be dissipated by each logicgate on the chip? If the average gate must switch at100 MHz, what is the maximum capacitive load ona gate for VDD =3.3 V, 2.5 V and 1.8 V.
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