Q4/ A- How many: 1- memory locations can be addressed by a microprocessor with 14 address lines? 2- chips are required to make up 1k byte of memory, If the memory chip size is 256 X 1 bits? 3- address line are necessary to address two megabytes (2048k) of memory? 4- bits are stored by a 256 X 4 memory chip? Can this chip be specified as 128 byte memory? 5- lines must be decoded to generate five chip select signals? B- What it is the addressing mode instructions in 8086, list it with examples.
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- Suppose that 16M × 16 memory built using 512K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved? 3. c) How many address bits are needed for each RAM chip?4. d) How many banks will this memory have?5. e) How many address bits are needed for all memory?6. f) If high-order interleaving is used, where would address 14 (which is E in hex) be located?7. g) Repeat exercise 9f for low-order interleaving.1. CPU with 2ns clock, hit time = 1 cycle, miss penalty = 40 cycles, cache hit rate = 90% AMAT = ___ ns.? 2. A memory system with cache memory has an 8-bit word address. Each memory block (or cache line) consists of 4 words. How many bits are used for the word offset in an address? 3. A memory system with cache memory has an 8-bit word address. The direct-mapped mapping technique is used. The cache memory has 8 cache blocks. How many bits are used for the block index field in an address?Suppose that a 2M × 16 main memory is built using 256K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved? 3. c) How many address bits are needed for each RAM chip?4. d) How many banks will this memory have?5. e) How many address bits are needed for all memory?6. f) If high-order interleaving is used, where would address 14 (which is E in hex) be located?7. g) Repeat exercise 9f for low-order interleaving.
- Suppose that a 64M x 16 main memory is built using 512K × 8 RAM chips and memory is word-addressable. a) How many RAM chips are necessary?b) If we were accessing one full word, how many chips would be involved?c) How many address bits are needed for each RAM chip?d) How many banks will this memory have?e) How many address bits are needed for all of memory?f) If high-order interleaving is used, where would address 32(base 10) be located? (Your answer should be "Bank#, Offset#")g) Repeat (f) for low-order interleaving.Suppose that a 4M × 32 main memory is built using 128K × 8 RAM chips and memory is word addressable (word size = 32 bits)a. How many RAM chips are needed?b. How many chips would be involved when accessing a full word?c. How many banks will this memory have?d. How many address bits are needed for the whole main memory?e. If high-order interleaving is used, where would the address 7060016 be located (in which bank)?f. If low-order interleaving is used, where would the address 2C77D516 be located?20. Which of the following statements is true of memory sizes? a. A 3 kb memory has 3000 memory bits b. A 16 × 4 memory has 64 words c. A 4 kb memory has 4096 memory bits d. A 32 × 16 memory has 16 words 21. Which of the following statements about cache is NOT true? a. A cache typically resides on-chip with the processor. b. A cache is faster and has higher capacity than memory. c. A cache hit means that an item is found in the cache. d. SRAM is faster than DRAM
- . Fully AssociativeParameters• Main Memory: 2 GB• Block/Line Size: 32 B• Cache: 1 MB Fully AssociativeQuestions• How many main memory blocks are there?• How many cache lines are there?• How many memory blocks map to a single cache line?• What is the address breakdown for RAM?Block Index Byte Offset• What is the address breakdown for cache?Tag Byte Offset• Lookup Algorithm for Address X:What would the following look like in memory? Write the data values in hex and continue numbering for the addresses. AREA MyData, DATA stuff dcb 15, 0x15, "1", -5 ; info space 4 things dcd 0xCD8912AB, -5, 0xFB, 0xF00D ;use our default endianness stuff2 dcb 4, 0, 0, 0xC Address (in hex) Data (in hex) Label 0x20000000 0x20000001 0x20000002 0x20000003 ...please help me. thank you Currently, in a PC equipped with 8 GByte of main memory, the CPU actually supports only 32-bit (4 GB) physical address space, but when the 40-bit (1 TB) virtual address space is supported for executing large-scale programs. , When the page size is 2KByte and 4 bytes per page table entry are used. 1) How many bytes is the sige of the page table allocated per process? 2) Explain why this processor configuration is practical. 3) How do I change which of the parameters given in the problem for this processor to be practical?
- please sol Q1) Given a memory of 16k and a cache memory of 1024 bytes with block size 128 bytes. Thesystem uses Direct mapping.A- How many blocks available in both physical memory and cache memory B- How the address will be split to indicate tag, line (block no) and offsetC- Calculate the cache line number and offset in cache that will contain the content ofmemory address 230.Suppose that a 64 Mega x 16 bits main memory is built using 16M x 8 bits chips of RAM and memory is word addressable. a. How many RAM chips are necessary? ______ b. How many RAM chips are needed for each memory word? _______ c. How many address bits are needed for each RAM chip? _______ d. How many address bits are needed for all memory? _______A computer is using a fully associative cache and has 216 bytes of main memory (byte addressable) and a cache of 64 blocks, where each block contains 32 bytes. a. How many blocks of main memory are there? b. What will be the sizes of the tag, index, and byte offset fields? c. To which cache set will the memory address 0xF8C9(hexadecimal) map?