
Database System Concepts
7th Edition
ISBN: 9780078022159
Author: Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher: McGraw-Hill Education
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Transcribed Image Text:Suppose a computer using fully associative cache has
2^24 bytes of byte-addressable main memory and a
cache of 128 blocks, where each block contains 64
bytes. How many blocks of main memory are there?
O 2^24
O 2^7
O 2^6
2^18
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- A 2-way set associative cache consists of four sets. Main memory contains 2K blocks of eight words each. Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes. Compute the hit ratio for a program that loops 6 times from locations 8 to 51 in main memory. You may leave the hit ratio in terms of a fraction. Please show details how you obtain the result.arrow_forwardSuppose we have a byte-addressable computer with a cache that holds 8 blocks of 4 bytes each. Assuming that each memory address has 8 bits, to which cache block would the hexadecimal address 0x2D map if the computer uses direct mapping? Blocks are numbered starting at 0arrow_forwardSuppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.Q.) To which cache block will the memory address 0x01D872 map?arrow_forward
- Question 23 Some portion of cache system A represented below. The system is byte-addressable and the block size is one word (4 bytes). The tag and line number are represented with a binary numbers. The contents of words in the block are represented with hexadecimal. Tag 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1001 10 1000 0100 1101 Line Number 0110 1101 0110 1110 0110 1111 B1 FF B8 A1 FF B8 B1 FF B8 A1 FF B8 B1 FF B8 0111 0000 1. What is the size of the main memory of this system? 2. What is the size of the cache memory of this system? 00 Word within block 2016 6116 C116 2116 01 10 11 3216 7216 C216 D216 4216 8216 4116 A216 E216 9216 5216 B216 3. If the CPU requests to read memory address A1 25 BA, what data does the CPU receive? 4. If the CPU requests to read memory address A1 35 C2, what data does the CPU receive? 5. If we access memory in the following order in cache system A: A1 FF B8 how many cache misses would occur for the data request?arrow_forwardYou are given a main memory of 64Mbytes with each byte addressable and asked to design a cache memory using direct mapping. The main memory is organized as blocks of 8bytes. The cache memory must have a size of 512Kbytes. How many lines do you need to use in the cache memory?arrow_forward
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