A Instruction Set ArchitectureA.1 Instruction setWe present a list of instructions typical of a RISC (reduced instruction set computer) machine. In data-movement and control instructions, the addresses may be immediate #X, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. Data-processing instructions use immediate or register addressing. PC is the programme counter and a <- b indicates that the value of b is placed in a. LOAD a, b a <- bSTOR a, b a <- bADD a, b, c a <- b + c ASH a, b, c a <- (b >>[s] c)LSH a, b, c a <- (b >>[u] c) BR a PC <- a SUBa,b,ca<-b- cBEQa,b,cPC<-aifb =cMULa,b,ca<-b* cBNEa,b,cPC<-aifnotb = cDIVa,b,ca<-b/ cBLTa,b,cPC<-aifb <cANDa,b,ca<-b& cBGTa,b,cPC<-aifb >c OR a, b, c a <- b | cNOT a, b a <- !b BLE a, b, c PC <- a if b <= c BGE a, b, c PC <- a if b >= c Note: Here b >>[s] c denotes the arithmetical shift of b to the right by c positions, andb >>[u] c denotes the logical shift of b to the right by c positions. A.2 The pipelineWe will use a five-stage pipeline:IF (instruction fetch),ID (instruction decode),RR (register read),EX (execute instruction),WB (write back result into register).Note that for some instructions (e.g., LOAD r, #X) some of the pipeline stages (e.g., RR) are not

The solution to the above problem will be : 1. LOAD r3, M //load n from the memory location M in r3…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

A Instruction Set Architecture

A.1 Instruction set

We present a list of instructions typical of a RISC (reduced instruction set computer) machine. In data-movement and control instructions, the addresses may be immediate #X, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. Data-processing instructions use immediate or register addressing. PC is the programme counter and a <- b indicates that the value of b is placed in a.

LOAD a, b a <- b

STOR a, b a <- b

ADD a, b, c a <- b + c

ASH a, b, c a <- (b >>[s] c)

LSH a, b, c a <- (b >>[u] c) BR a PC <- a

SUB

- c

BEQ

b =

MUL

* c

BNE

not

b = c

DIV

/ c

BLT

b <

AND

& c

BGT

b >

OR a, b, c a <- b | c

NOT a, b a <- !b

BLE a, b, c PC <- a if b <= c BGE a, b, c PC <- a if b >= c

Note: Here b >>[s] c denotes the arithmetical shift of b to the right by c positions, and

b >>[u] c denotes the logical shift of b to the right by c positions.

A.2 The pipeline

We will use a five-stage pipeline:

IF (instruction fetch),
ID (instruction decode),
RR (register read),
EX (execute instruction),
WB (write back result into register).
Note that for some instructions (e.g., LOAD r, #X) some of the pipeline stages (e.g., RR) are not

Expert Solution

Step by step

Solved in 2 steps

SEE SOLUTION Check out a sample Q&A here

Knowledge Booster

Learn more about

Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, computer-science and related others by exploring similar questions and additional content below.

Similar questions