A. Cache coherency and false sharing The simplest cache coherency protocol is MESI. Although cache coherency is important for making sure a program executes correctly, it leads to false sharing, which can cause performance problems. In order to remove false sharing, we have to either move variables in memory so that they fit in different cache lines or Align shared global data to cache line boundaries. For example, in the situation shown in this code: struct foo { int xi int Vi } ; int numThreads = 2; struct foo z; if (threadID ==0) { int suml = 0; int ii for (i = 0; i < 100000; ++i) sum1 += z. x; } www if (threadID ==1) { int sum2 0; int ii for (j = 0; j < 100000; ++j) sum2 += z.y;}

A. Cache coherency and false sharing The simplest cache coherency protocol is MESI. Although cache coherency is important for making sure a program executes correctly, it leads to false sharing, which can cause performance problems. In order to remove false sharing, we have to either move variables in memory so that they fit in different cache lines or Align shared global data to cache line boundaries. For example, in the situation shown in this code: struct foo { int xi int Vi } ; int numThreads = 2; struct foo z; if (threadID ==0) { int suml = 0; int ii for (i = 0; i < 100000; ++i) sum1 += z. x; } www if (threadID ==1) { int sum2 0; int ii for (j = 0; j < 100000; ++j) sum2 += z.y;}

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

See similar textbooks

Similar questions

CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
A two-level cache hierarchy of L1 and L2 with 2 and 3 blocks respectively is designed. Both L1 and L2 are fully-associative with LRU replacement policy. A sequence of references (block addresses from left to right, denoted as letters) is given in the table. Both caches are empty initially. You need to simulate the contents of L1 and L2 for the given sequence. Note that each request goes to L1 first. A request is issued to L2 only if it misses L1. In case of a L2 hit, the requested block is fetched from L2 and placed into L1, both in the MRU position. In case of a L2 miss, the block is loaded from memory into both L1 and L2 caches in the MRU position. The cache contents are displayed by the block addresses from MRU position to LRU position, separated by a comma.
For a direct-mapped cache design with a 32-bit address, the following bits ofthe address are used to access the cache. We assume that each word has 4 bytes. Hints:this is a multiword block direct-mapped cache because each cache block (i.e., each cacheline or each cache entry) contains multiple words. The width of the “Byte offset” segmentis 2 (i.e., the lowest two bits of a 32-bit address), which indicates that each word has 4bytes. The width of the “Block offset” segment (i.e., from the 2nd bit to the 5th bit of a 32-bit address) determines the number of words per cache line. A) What is the cache line size (in words)? B) How many entries does the cache have? C) What is the ratio between total bits required for such a cacheimplementation over the data storage bits?
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache.Tag Index Offset31–10 9–5 4–01. What is the cache block size (in words)?2. How many entries does the cache have?3. What is the ratio between total bits required for such a cache implementation over the data storage bits?Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 How many blocks are replaced? What is the hit ratio? List the fi nal state of the cache, with each valid entry represented as a record of <index, tag, data>
Describe why it is difficult to implement a cache replacement policy that is optimal for all address sequences.
Now, we consider a 16-byte, four-way, fully-associative cache. Since the capacity of the cache is 16 bytes, the array "a" in our example (does/does not) fit inside the cache. We can deduce that the block size for this cache is ( ？ ) bytes per block. So the block index size b=2 bits. For a memory trace record such as: L 1fff000116,2 the 2-bit block offset is (0b01/0b10/0b11/0b00). The tag bits are all the rest of the bits not part of the block offset.
Describe the problems encountered while trying to build a cache replacement technique that is optimal for all addresses.
Recall that we have two write policies and write allocation policies, and their combinations can be implemented either in L1 or L2 cache. Assume the following choices for L1 and L2 caches: L1 L2 Write through, non-write allocate Write back, write allocate 1. Buff ers are employed between diff erent levels of memory hierarchy to reduce access latency. For this given confi guration, list the possible buff ers needed between L1 and L2 caches, as well as L2 cache and memory.2. Describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.3. For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches), confi guration, describe the procedure of handling an L1 write-miss, considering the component involved and the possibility of replacing a dirty block.Consider the following program and cache behaviors. Data Reads per1000 Instructions Data Writes per1000 Instructions Instruction…
Suppose we have a system with the following properties:The memory is byte addressable.Memory accesses are to 1-byte words (not to 4-byte words).Addresses are 13 bits wide.The cache is 4-way set associative (E = 4), with a 4-byte block size(B = 4) and eight sets (S = 8).Consider the following cache state. All addresses, tags, and valuesare given in hexadecimal format. The Index column contains the set index for each set of four lines. The Tag columns contain the tag value for each line. The V columns contain the valid bit for each line. The Bytes 0−3 columns contain the data for each line, numbered left to right starting with byte 0 on the left. A. What is the size (C) of this cache in bytes?B. The box that follows shows the format of an address (1 bit perbox). Indicate (by labeling the diagram) the fields that would beused to determine the following:CO. The cache block offsetCI. The cache set indexCT. The cache tag
Give an example in the miss rate table where higher set associativity actually increases miss rate. Construct a cache configuration and reference stream to demonstrate this.
For a direct-mapped cache design with a 32-bit address, the following bits of the address areused to access the cache.Tag Index Offset31–10 9–6 5–0a– What is the cache block size (in words)? b – How many entries does the cache have? c – What is the ratio between total bits required for such a cache implementation overthe data storage bits?
In this exercise, we will examine space/time optimizations for page tables. The following list provides parameters of a virtual memory system. Virtual Address (bits) Physical DRAMInstalled Page Size PTE Size (byte) 43 16 GiB 4 KiB 4 For a single-level page table, how many page table entries (PTEs) are needed? How much physical memory is needed for storing the page table? Using a multilevel page table can reduce the physical memory consumption of page tables, by only keeping active PTEs in physical memory. How many levels of page tables will be needed in this case? And how many memory references are needed for address translation if missing in TLB? An inverted page table can be used to further optimize space and time. How many PTEs are needed to store the page table? Assuming a hash table implementation, what are the common case and worst case numbers of memory references needed for servicing a TLB miss?