Q5 Cache Performance Analysis This challenging question tests your understanding of cache. Consider the following C code: int A[16]; int B[16]; int m; ... //A large chunk of code that does NOT access //arrays A and B. ... for (int i=0; i<10; i++) { for (int j=0; j<16; j++) { B[j] = m * A[j] + B[j]; } } Assume this program runs on a 32-bit machine, i.e., the CPU loads/stores 4 bytes from memory in one go. This machine has a 16-bit memory address, and each memory block stores 16 bytes. This machine has a direct-mapped data cache with 16 cache lines. Array A starts at address 0, and B starts at address 256 - both arrays begin at a memory block boundary. Each element of arrays A and B occupies 4 bytes. The values of i, j, and m are stored in CPU registers. Assume we change the cache configuration to be 2-way set-associative. This new data cache has 8 sets and 16 bytes per line. The cache uses a Least Recently Used (LRU) replacement policy. How many data cache misses (including compulsory misses) will occur when running the above code with this new data cache design?

Q5 Cache Performance Analysis This challenging question tests your understanding of cache. Consider the following C code: int A[16]; int B[16]; int m; ... //A large chunk of code that does NOT access //arrays A and B. ... for (int i=0; i<10; i++) { for (int j=0; j<16; j++) { B[j] = m * A[j] + B[j]; } } Assume this program runs on a 32-bit machine, i.e., the CPU loads/stores 4 bytes from memory in one go. This machine has a 16-bit memory address, and each memory block stores 16 bytes. This machine has a direct-mapped data cache with 16 cache lines. Array A starts at address 0, and B starts at address 256 - both arrays begin at a memory block boundary. Each element of arrays A and B occupies 4 bytes. The values of i, j, and m are stored in CPU registers. Assume we change the cache configuration to be 2-way set-associative. This new data cache has 8 sets and 16 bytes per line. The cache uses a Least Recently Used (LRU) replacement policy. How many data cache misses (including compulsory misses) will occur when running the above code with this new data cache design?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 22VE

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Q5 Cache Performance Analysis This challenging question tests your understanding of cache. Consider the following C code: int A[16]; int B[16]; int m; ... //A large chunk of code that does NOT access //arrays A and B. ... for (int i=0; i<10; i++) { for (int j=0; j<16; j++) { B[j] = m * A[j] + B[j]; } } Assume this program runs on a 32-bit machine, i.e., the CPU loads/stores 4 bytes from memory in one go. This machine has a 16-bit memory address, and each memory block stores 16 bytes. This machine has a direct-mapped data cache with 16 cache lines. Array A starts at address 0, and B starts at address 256 - both arrays begin at a memory block boundary. Each element of arrays A and B occupies 4 bytes. The values of i, j, and m are stored in CPU registers. What is the total number of data cache misses (including compulsory misses) when running the above code?
Computer Science Consider a direct-mapped cache with 8 lines, each holding 16 bytes of data. The cache is byte-addressable and the main memory consists of 64 KB, which is also byte-addressable. Assume that a program reads 16KB of memory sequentially. Answer the following questions:a) How many bits are required for the tag, index, and offset fields of a cache address?b) What is the cache size in bytes?c) What is the block size in bytes?d) What is the total number of blocks in main memory?e) How many cache hits and misses will occur for the program, assuming that the cache is initially empty?f) What is the hit ratio?g) Give an example virtual address (in BINARY) that will be placed in cache line 5.
Cache Memory Caches depend on the locality principle – if you access memory locations near to each other, then you will get better performance because the cache will pull in a bunch of nearby locations every time you access main memory. Assume that multi-dimensional arrays in C are stored in “row major order”, that is, the elements in each row are stored together Example: int test[3][5] = { {1, 2, 3, 4, 5}, {6, 7, 8, 9, 10}, {11, 12, 13, 14, 15} } Would be laid out in memory like: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Which of these two programs fragments (a or b) should have better cache performance? You need only answer “a” or “b” – no explanation needed. // begin fragment a int big[100,1000]; for (i=0, i<100, i++) { for (j=0, j<999, j++) { big[i,j] += big[i,j+1]; } } // end fragment a // begin fragment b int big[100,1000]; for (j=0, j<999, j++) { for (i=0, i<100, i++) { big[i,j] += big[i,j+1]; } } // end fragment b
Q.A direct-mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main memory is 300ns. (This time allows us to determine that the block is missing and bring it into cache.) Assume that a request is always started in parallel to both cache and to main memory (so if it is not found in cache, we do not have to add this cache search time to the memory access). If a block is missing from cache, the entire block is brought into the cache and the access is restarted. Initially, the cache is empty.Q.) Compute the hit ratio for a program that loops four times from addresses 0x0 to 0x43 in memory.
For a direct-mapped cache design with a 32-bit address, the following bitsof the address are used to access the cache. Use the table below. a. What is the cache block size (in words)?b. How many entries does the cache have?c. What is the ration between total bits required for such a cache implementation overthe data storage bit?
CA_6 We study the properties of cache memory, and for reasons of easier design and efficient circuits, we assume that the cache capacity is 2i Bytes, and cache line size is 2j Bytes, with i and j being natural numbers: (a) How many bits should the tag field have? And can the tag field contain 0 bit (i.e., be empty)? Elaborate (b) Repeat the above for the index field. (c) Repeat the above for the byte-offset field. (d) Finally, depict a figure showing a cache line, indicate what fields it possibly has, state the possible sizes of these fields, and explain the uses of these fields.
Cache Mapping Technique 1. Suppose a computer usingdirect-mapped cache has 2 bytes of byte=addressable main memory and a cache of32 blocks, where each cache block contains 16 bytes.a) How many blocksof main memory are there?b) What is theformat of a memory address as seen by the cache; that is, what are the sizes ofthe tag, block, and offset fields?c) To which cacheblock will the memory address 0x0DB63 map?2. Suppose a computer using fullyassociative cache has 2 bytes of byte-addressable main memory and a cache of128 blocks, where each cache block contains 64 bytes.a) How many blocksof main memory are there?b) What is theformat of a memory address as seen by the cache; that is, what are the sizes ofthe tag and offset fields?c) To which cacheblock will the memory address 0x01D872 map?3. A 2-way set-associative cacheconsists of four sets. Main memory contains 2K blocks of 8 bytes each and byte addressingis used.a) Show the mainmemory address format that allows us to map addresses from…
Describe the challenges that arise when attempting to build a cache replacement approach that works for all address sequences.
For a direct-mapped cache design with a 32-bit address, the following bits ofthe address are used to access the cache. We assume that each word has 4 bytes. Hints:this is a multiword block direct-mapped cache because each cache block (i.e., each cacheline or each cache entry) contains multiple words. The width of the “Byte offset” segmentis 2 (i.e., the lowest two bits of a 32-bit address), which indicates that each word has 4bytes. The width of the “Block offset” segment (i.e., from the 2nd bit to the 5th bit of a 32-bit address) determines the number of words per cache line. A) What is the cache line size (in words)? B) How many entries does the cache have? C) What is the ratio between total bits required for such a cacheimplementation over the data storage bits?
Caches are important to providing a high-performance memory hierarchy toprocessors. Below is a list of 32-bit memory address references, given as word addresses.4, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253 a. For each of these references, identify the binary address, the tag, and the indexgiven a direct-mapped cache with 16 one-word blocks. Also list if each reference is a hitor a miss, assuming the cache is initially empty.b. For each of these references, identify the binary address, the tag, and the indexgiven a direct-mapped cache with two-word blocks and a total size of 8 blocks. Also listif each reference is a hit or a miss, assuming the cache is initially empty.
The essential distinction between a genuinely associative cache and a directly mapped cache is the capacity to flexibly associate data elements.
"Spatial locality" and "temporal locality" boost performance with caches. These two events benefit caches.