Suppose that immediately following the two read operations of question 1, the program does read operations on the following memory addresses (e.g., with “lb” or “lw” instructions): 168, 500, 100, 232, and 168 (again). Assuming the cache was empty prior to the read operations of question 1, and LRU replacement for the set associative caches, state which of these read operations will result in cache hits, if any, for each of the following cache configurations. (a) direct-mapped with total cache capacity of 16 one-word blocks (b) direct-mapped with total cache capacity of 4 four-word blocks (c) 4-way set associative with total cache capacity of 16 one-word blocks (d) 2-way set associative with total cache capacity of 4 four-word blocks
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Suppose that immediately following the two read operations of question 1, the program does read operations on the following memory addresses (e.g., with “lb” or “lw” instructions): 168, 500, 100, 232, and 168 (again). Assuming the cache was empty prior to the read operations of question 1, and LRU replacement for the set associative caches, state which of these read operations will result in cache hits, if any, for each of the following cache configurations. (a) direct-mapped with total cache capacity of 16 one-word blocks
(b) direct-mapped with total cache capacity of 4 four-word blocks
(c) 4-way set associative with total cache capacity of 16 one-word blocks (d) 2-way set associative with total cache capacity of 4 four-word blocks
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