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- Consider a memory-management system based on paging. The total size of the physical address space 64 MB, Pages of size 4 KB, the Logical address space of 4GB. total number of pages are 16384, total number of frames are 16384 and the number of entries in a page table are 1048576.Now Calculate: a)Size of Page Table b) No of bits in Physical Address c) No of Bits in Logical AddressConsider a processor that uses a 48-bit virtual memory address. The main memory installed onthe system is 4GB. Page size is set to be 32KB. Determine the following:I. Address space of virtual memory and physical memory. II. Total Number of virtual pages and the total physical pagesIII. How many bits are necessary to store (i) Page Table entry and (ii) TLB entry, consideringthe TLB entry stores valid, reference and dirty bits.IV. What is the size of the page table? And how many pages of memory is needed to storethe entire Page table? What fraction of physical memory is needed to store the entirepage table?For an old computing system with 2K bytes physical memory, and the virtual address has 13bits. Suppose that the size of page/frame is 256 bytes. For a process A, it has its codes and data inpage 0, 1, 2, 10, 11, 28, 29, where pages 0, 1, 10, 29 are in frame 1, 3, 4 and 6, respectively.Moreover, frame 0 contains kernel OS code/data and all other frames are free.a. Show the page table and the content of each PTE for process A;b. Use a figure to illustrate the address translation for virtual address 1110000100000 and explainwhat happens during the translation (interaction among page table, physical memory, disk, andoperating system);c. Suppose that there is a TLB with 4 entries and the current content has the mapping informationfor pages 0, 1. Draw a new figure to illustrate the translation of address 101000011000 andexplain what happens during the translation process.
- Consider a process with 4GB logical memory, 4KB page size, and a page table whose entry is 4B each. The page table of this process will be placed in one of the cache memories to increase performance. The size of L1, L2, and L3 caches are 64KB, 256KB, and 8MB, respectively. Investigate which cache memory can we use to fully place the page table.In an architecture with 18 bits of "virtual address" width, "page size" is given as 1024 bytes and "physical address" width is given as 15 bits. TLB has a “2-way set associative” structure and contains a total of 16 data blocks. What is the TLB Tag field width in this architecture? A) 4 B) 5 C) 6 D) 7 E) 8Suppose that a machine has 42-bit virtual addresses and 32-bit physical addresses.{a} How much RAM can the machine support (each byte of RAM must be addressable)?{b} What is the largest virtual address space that can be supported for a process?{c} If pages are 2 KB, how many entries must be in a single-level page table?{d} If pages are 2 KB and we have a two-level page table where the first level is indexed by 15-bits, then how many entries does the first-level page table have?{e} With the same setup as part {d}, how many entries are in each second-level page table?{f} What is the advantage of using a two-level page table over single-level page table?
- Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?Consider an operating system using memory mapping on a page basis and using a single level page table. Assume that the necessary page table is always in memory. The system takes 200 ns to make a memory reference, how long does a paged memory reference take? Group of answer choices 400 ns (nanoseconds) 809.2 ms (microseconds) 200 ns (nanoseconds) 1638.4 ms (microseconds)Consider a paging system with the page table stored in memory.a. If a memory reference takes 400 nanoseconds, how long does a paged memoryreference take?b. If we add TLBs, and 95 percent of all page-table references are found in the TLBs,what is the effective memory reference time? (Assume that finding a page-table entry inthe TLBs takes zero time, if the entry is there.)
- 4. Given that the main memory size is 32KB, the page size is 64B, the word size is 1B, and n-level paging is applied. What is the page number size? If (5, 10) is a record in the outer page table stored in PCB and (9, 7) is a record in the inter page table stored in page frame No.10, what is the physical address of the logical address 0010101001000110 in HEX?Suppose a two layer memory hierarchy has a 4 clock pulse hit time, a 35 clock pulse miss penalty, and the miss ratio is 20%. What is the AMAT (in number of clock pulses)?Suppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. 8 bits are used for offset, 8 bits are used for page # and the max number of pages a process can have is 256. e. Translate the following virtual addresses to physical addresses, and show how you obtain the answers. (Hint: You do not need to convert hexadecimal numbers to decimal ones.) 0x0389 0xDF78 0x0245 0x8012 f) Now, suppose that the OS uses a two-level page table. Draw the page table. (Assume that frames 7 through 221 are free, so you can allocate space for the page table there.) In addition, suppose that the page-table directory storage comprises a whole number of consecutive full frames. (For examples: if the directory entry is 2 bytes, the entry’s storage comprises 1 frame; if the directory entry is 260 bytes, the entry’s storage comprises 2 consecutive frames.) g)What is the size of the two-level page table…