the AMAT (in number of clock pulses)?
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Suppose a two layer memory hierarchy has a 4 clock pulse hit time, a 35 clock pulse miss penalty, and the miss ratio is 20%. What is the AMAT (in number of clock pulses)?
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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?Consider a memory system with a cache access time of 100ns and a memory access timeof 1200ns. If the effective access time is 10% greater than the cache access time, what is thehit ratio H?Consider the following situation: we have a byte-addressable computer with 2-way set associative mapping, 16-bit main memory addresses, and 32 blocks of cache memory. Based on the fact that each block has 8 bytes, figure out how big the offset field should be, and then show your work.
- Suppose a byte-addressable computer using set associative cache has 2^24 bytes of main memory and a cache size of 64K bytes, and each cache block contains 32 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?Consider a computer which uses virtual addressing with 32 bit addresses and a two level page table. The virtual addresses are split into a 9 bit top level page table field, an 11 bit second level page table field and an offset. How large are the pages and, how many are there in the address space?Suppose we have a system with 8-byte words and a cache with 32-byte blocks connected directly to memory. The cache has a hit time of 10 ns. The bus to memory is 8 bytes wide, requesting a word from memory takes 100 ns (total, aka round trip time), and memory bus transactions are serialized (not pipelined). The baseline cache requests each word from memory sequentially on a miss, and waits to respond to the CPU until miss repair is fully complete. Consider a workload with poor locality, with a cache hit rate of only 20%. Show your work. (a) What is the AAT speedup of early restart over baseline? Assume a uniform distribution of accesses to each word in a block (25% chance of each). This means that 25% of misses are for word 1 in a block, 25% for word 2, 25% for word 3, and 25% for word 4. (b) What is the AAT speedup over baseline of early restart if the distribution of accesses to each word in a block is 5%, 15%, 30%, and 50%, respectively? (c) What is the AAT speedup over baseline with…
- Consider a system with the following specifications: 46-bit virtual address space Page size: 8 KB Page table entry size (PTE): 4 bytes How many levels should a multi-level page table have, if the page table at each level must fit into a single page ? Explain.Suppose we have a virtual address of 26 bits in a byte addressable machine. Page size is 8K bytes. Assume each page table entry is 4 bytes in this case. a. Design a two-level page table (Suppose we need to fit each page table into a physical frame). b. How many physical memory frames are needed to maintain the page tables for a process of 512KB?In an architecture with 18 bits of "virtual address" width, "page size" is given as 1024 bytes and "physical address" width is given as 15 bits. TLB has a “2-way set associative” structure and contains a total of 16 data blocks. What is the TLB Tag field width in this architecture? A) 4 B) 5 C) 6 D) 7 E) 8
- If we assume each page is 1Kbyte (2^10), for a 32 bit system with the 4GB(2^32) virtual address face each of the pages is Matt by eight to bite page table injury. What is the storage speed required for the page table of the processSuppose a byte-addressable computer using set associative cache has 8M byes of main memory and a cache of 128 blocks, where each cache block contains 64 bytes. a) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 16-way set associative, what is the format of a memory address as seen by the cacheSuppose a byte-addressable computer using set associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes. a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache, that is, what are the sizes of the tag, set, and offset fields? b) If this cache is 4-way set associative, what is the format of a memory address as seen by the cache?