Carefully study the following logic circuit and answer the next three questions. If Reset= 0, S1S0 = 11,D3D2D1D0 = 1111, Q3Q2Q1Q0 = 0100, at the next positive-edge of the clock, then binary output at Q3Q2Q1Q0 will be Blank 1 .      If Reset= 0, S1S0 = 11,D3D2D1D0 = 1011, Q3Q2Q1Q0 = 0101, at the next positive-edge of the clock, then binary output at Q3Q2Q1Q0 will be Blank 2 .       If Reset= 0, S1S0 = 11,D3D2D1D0 = 1000, Q3Q2Q1Q0 = 0110, at the next positive-edge of the clock, then binary output at Q3Q2Q1Q0 will be Blank 3 .

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter4: Processor Technology And Architecture
Section: Chapter Questions
Problem 9VE
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Question 5
 

Carefully study the following logic circuit and answer the next three questions.

  • If Reset= 0, S1S0 = 11,D3D2D1D0 = 1111, Q3Q2Q1Q0 = 0100, at the next positive-edge of the clock, then binary output at Q3Q2Q1Q0 will be Blank 1 .     
  • If Reset= 0, S1S0 = 11,D3D2D1D0 = 1011, Q3Q2Q1Q0 = 0101, at the next positive-edge of the clock, then binary output at Q3Q2Q1Q0 will be Blank 2 .      
  • If Reset= 0, S1S0 = 11,D3D2D1D0 = 1000, Q3Q2Q1Q0 = 0110, at the next positive-edge of the clock, then binary output at Q3Q2Q1Q0 will be Blank 3 .     
Parallel Inputs
D3
D2
D1
Do
Right
Left
Serial Input
Serial Input
3 210
3210/
3 2 104
32 10
S
D
D
R Q
RQ
R Q
R Q
Clock
Reset
Q3
Q2
Q1
Qo
Parallel Outputs
Transcribed Image Text:Parallel Inputs D3 D2 D1 Do Right Left Serial Input Serial Input 3 210 3210/ 3 2 104 32 10 S D D R Q RQ R Q R Q Clock Reset Q3 Q2 Q1 Qo Parallel Outputs
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