cmpl $4 , %edi movl %edi , %edi jmp .L4(,%rdi,8) .L3: movl $17, %eax ret .L5: movl $3, %eax int A ( int x , int y) { int a ; ret .L6: if ( x else i f ( x else i f ( x == else i f ( x else i f ( x == 4 ) a = 17; ) a 2 ) a 3 ) a == a = movl $20, %eax 3 ; %3D%3D ret 2 0 ; %3D .L7: 2 ; %3D%3D %3D movl $2, %eax 1 ; a = 0; ret else .L8: return a ; movl $1. %eax
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- 25: . Find the time delay in the following program if the crystal frequency is 1 MHz. Do not ignore the time delay due to the first and last instruction. DELAY: LDI R16, 30 AGAIN: LDI R17, 35 HERE: NOP NOP DEC R17 BRNE HERE DEC R16 BRNE AGAIN RET 26: Write a program to display 2 on 7 segment. A 7 segment is connected to PortD.Consider the following LEGv8 assembly code. Show the corresponding C code segment for the code below. Assume that the C-level integer i is held in register X10,X0 holds the C-level integer called result, and X1 holds the base address of the data array.AND X10, XZR, XZRLOOPFOR:LDUR X11, [X1, #0]ADD X0, X0, X11ADDI X1, X1, #8ADDI X21, X21, #1CMPI X21, 100B.LT LOOPFORSuppose a specific MCU has the following size of memories: 2 M byte of flash, starting from 0x0800_0000, 256 k byte of SRAM starting from 0x2000_0000, and 8 k byte registers for GPIOs, start at 0x4001_0000. (Note that 0x is the prefix for hexadecimal numbers.) Draw the memory map based on your calculations for the addresses.
- The multicand of a multiplication operation is located at the memory adress 1190H and the multiplier is located at 1191H. Write a 8085 program using minimum number of instructions, I) First, to copy those numbers to HL register pair, II) Then, call the subroutine to make the multiplication and store the result at the memory adress 2291H. Write a function (subroutine) called MULT using minimum number of instructions, I) First, to do the multiplication of those numbers in the H and L register pair, II) Return the result to the H and L pair. Important: Your codes should be exactly correct such that they will be run in simulator without any error.In the Intel 8086 microprocessor, suppose the register AX contains the data 35AB H. What will be the contents of AX after executing the following programs? Assume that the initial content on the Carry Flag (CF) is one for all the calculations. You MUST clearly show ALL your steps in obtaining your final result for getting full and/or partial credit. Please present your final result in Hexadecimal format. (a) MOV CL,04H SHR AX,CL RET (b) MOV CL,04H RCR AX,CL RETFor the MIPS assembly instructions below, what is thecorresponding C statement? Assume that the variables f, g, h, i, and j areassigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume thatthe base address of the arrays A and B are in registers $s6 and $s7,respectively. Note: for each line of MIPS code below, write the respective Ccode. After that, write the corresponding C code for the MIPS.sll $t0, $s0, 2add $t0, $s6sll $t1, $s1, 2 add $t1, $s7, $t1lw $s0, 0($t0)addi $t2, $t0, 4lw $t0, 0($t2)add $t0, $t0, $s0sw $t0, 0($t1)
- If R0 = 0x8000 and memory data layout is as below, what are the r1 and r0 register values, respectively, after LDR r1, [r0], #4 instruction (data layout big endian)? A. r1= 0x1A2CEB0D, r0 = 0x8000 B. r1=0x0dEB2C1A, r0 = 0x8000 C. r1=0x79CDA3FD, r0 = 0x8000 D. r1= 0x1A2CEB0D, r0 = 0x8004 E. r1= 0x79CDA3FD, r0 = 0x8004The register content for an Intel 8086 microprocessor is as follows:CS = 1000H, DS = 2000H, SS = 5000H, SI = 2000H, DI = 4000HBX = 6783H, BP = 7000H, AX = 29FFH, CX = 8793H, DX = A297HCalculate the physical address of the memory where the operand is stored and the contents of the memory locations in each of the addresses shown below: a) MOV [SI], ALb) MOV [DI+6H], BXc) MOV [SI+BX–11], AXd) MOV [DI][BX]+28H, CXe) MOV [BP][SI]+17, DXAssume that the operation times of one add instruction for the major functional units are 325 ps for memory access, 185 ps for ALU operations and 125 ps for register file read/writes. Please fill the table first and perform the following a )What is the total cycle in single-cycle implementation? b )What is the total cycle in pipelining implementation? c) What is the total cycle in pipelining implementation if there are 5 million add instructions? d) What is the total cycle in pipelining implementation for 5 million add instructions, if the stages are balanced? e)What is the speed up of pipelining implementation over single-cycle implementation?
- cs 218 assembly language Given the code fragment: list db 3, 2, 1, 3, 5, 4, 2, 5 mov rbx, list mov rsi, 5 mov rdx, 0 mov rcx, 3 inc rsi mov byte [list+4], 3 lp: mov al, byte [rbx+rsi] mul al add dx, ax sub rsi, 2 loop lp What would be in the word sized ax, and dx registers after execution (in hex)? ax dx Must answer in hex (must precede number with 0x).Which of the following attributes is associated with RISC architecture? Group of answer choices a) AMD64/Intel64/X86-64 is an example of a RISC ISA b) Each instruction does as much computation as possible so that instruction fetch and decode overhead is relatively small c) Instructions tend to use very simple encoding, often fixed length d) Instructions like add can have one operand accesed directly from memory e) Arguments to functions are always passed on the stackOn a uniprocessor, portion A of program P consumes 24 seconds, while portion B consumes 822 seconds. On a parallel computer, moderately serial portion A speeds up 4 times, while perfectly parallel portion B speeds up by the number of processors. 1- What is the speedup of program P on 1,024 processors? _______ times 2- How many processors are required to achieve at least half the theoretical maximum possible speedup on P?