Our system is using virtual memory and has 48-bit virtual address space and 32-bit physical address space. Page size is 8 KiB. (a) How many entries are needed for a single-level page table? What does the two-level page table look like if the part of the virtual address which identifies the page number is split into two fields, such that the second part has 3 bits more than the first part?

Our system is using virtual memory and has 48-bit virtual address space and 32-bit physical address space. Page size is 8 KiB. (a) How many entries are needed for a single-level page table? What does the two-level page table look like if the part of the virtual address which identifies the page number is split into two fields, such that the second part has 3 bits more than the first part?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter6: System Integration And Performance

Section: Chapter Questions

Problem 12RQ

See similar textbooks

Similar questions

If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
Suppose that a machine has 38-bit virtual addresses and 32-bit physical addresses.(a) What is the main advantage of a multilevel page table over a single-level one?(b) With a two-level page table, 16-KB pages, and 4-byte entries, how many bits should be allocated for the top-level page table field and how many for the next-level page table field? Explain.
On a simple paging system with 224 bytes of physical memory, 256 pages of logical address space, and a page size of 210 bytes. 1. How many bits are needed to store an entry in the page table (how wide is the page table)? Assume a valid/invalid 1-bit is included in each entry. 2. If the page table is stored in the main memory with 250nsec access time, how long does a paged memory reference take? 3. If the page table is implemented using associative registers that takes 95nsec. and main memory that takes 200nsec, what is the total access time if 75% of all memory references find their entries in the associative registers?
Suppose that a machine has 42-bit virtual addresses and 32-bit physical addresses.{a} How much RAM can the machine support (each byte of RAM must be addressable)?{b} What is the largest virtual address space that can be supported for a process?{c} If pages are 2 KB, how many entries must be in a single-level page table?{d} If pages are 2 KB and we have a two-level page table where the first level is indexed by 15-bits, then how many entries does the first-level page table have?{e} With the same setup as part {d}, how many entries are in each second-level page table?{f} What is the advantage of using a two-level page table over single-level page table?
(b) Consider a paging system with the page table stored in memory. If a memory referencetakes 200 nano seconds, how long does a paged memory reference take? If we add a TLB,and 75% of all page references are found in the TLB, what is the effective memory referencetime? (Assume that it takes zero time to find an entry in the TLB if it is already present).
Consider a computer which uses virtual addressing with 32 bit addresses and a two level page table. The virtual addresses are split into a 9 bit top level page table field, an 11 bit second level page table field and an offset. How large are the pages and, how many are there in the address space?
Assume a 32-bit address system that uses a paged virtual memory, with a page size of 2 KB, and a PTE (Page Table Entry) size of 1 B. Answer the following questions, assuming a virtual address 0x00030f40 a. What is the virtual page number (VPN) and the offset in binary for the given virtual address? b. How many virtual pages are there in the system?
Assume a 32-bit address system that uses a paged virtual memory, with a page size of 2 KB. Answer the following questions, assuming a virtual address 0x00030f40 A. What is the virtual page number (VPN) and the offset in binary for the given virtual address? B. How many virtual pages are there in the system?
A computer with a 32-bit address uses a two-level page table. Virtual addresses are split into a 9-bit top-level page table field, an 11-bit second-level page table field, and an offset. How large are the pages and how many are there in the address space?
Suppose a computer using direct mapped cache has 4G Bytes of main memory and a cache of 256 Blocks, where each cache Block has 16 Words, and Word Size is 4 Bytes. a)How many blocks of main memory? b)What is the format of a memory address as seen by the cache (Tag, Block and Word fields)? c)To which cache block will the memory reference 0000146A in Hex?
4. Given that the main memory size is 32KB, the page size is 64B, the word size is 1B, and n-level paging is applied. What is the page number size? If (5, 10) is a record in the outer page table stored in PCB and (9, 7) is a record in the inter page table stored in page frame No.10, what is the physical address of the logical address 0010101001000110 in HEX?
Consider a logical address space of 256 pages with a 4-KB page size, mapped onto a physical memory of 64 frames. a. How many bits are required in the logical address? b. How many bits are required in the physical address?