For a direct-mapped cache design with 64-bit addresses, the following bits of the address are used to access the cache: Tag  Index Offset 63-13 12-4 3-0 a.  What is the cache block size (in bytes)? b.  What is the cache size (in bytes)? c.  What is the total number of bits (including valid bit, tag bits and data array bits) to implement this cache?

Computer Networking: A Top-Down Approach (7th Edition)
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Author:James Kurose, Keith Ross
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Chapter1: Computer Networks And The Internet
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For a direct-mapped cache design with 64-bit addresses, the following bits of the address are
used to access the cache:

Tag  Index Offset
63-13 12-4 3-0

a.  What is the cache block size (in bytes)?
b.  What is the cache size (in bytes)?
c.  What is the total number of bits (including valid bit, tag bits and data array bits) to
implement this cache?
d. For the same block and cache sizes, you want to implement a 4-way set-associative
cache, what is the number of index bit and the number of tag bits?

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