Given a system with 2 memory channels and 4 DRAM DIMMs (2 DIMMs per channel), each DIMM has: • 1 rank per DIMM • 8 chips per rank • 8 bits per column • 8 banks per chip 32,768 rows per bank • 2,048 columns per bank A) What is the total amount (bytes) of physical memory in the system? B) What is the minimum number of physical address bits needed to address this much memory? C) With the number of physical address bits obtained in 2), also assume • The physical address space has 1M (i.e., 1048576) pages (physical frames) • Virtual addresses have 64 bits What is the maximum number of pages in the virtual address space?

Given a system with 2 memory channels and 4 DRAM DIMMs (2 DIMMs per channel), each DIMM has: • 1 rank per DIMM • 8 chips per rank • 8 bits per column • 8 banks per chip 32,768 rows per bank • 2,048 columns per bank A) What is the total amount (bytes) of physical memory in the system? B) What is the minimum number of physical address bits needed to address this much memory? C) With the number of physical address bits obtained in 2), also assume • The physical address space has 1M (i.e., 1048576) pages (physical frames) • Virtual addresses have 64 bits What is the maximum number of pages in the virtual address space?

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 2PE: If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the...

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
Consider a cache memory with blocks of 23 words (1 word = 4 bytes) , with a bus Main Memory - Cache of (23x 32) bits , and with 1 clock cycle to send the address, a row cycle time (DRAM) of 13 cycles (one column only) and 1 clock cycle to return a word. Calculate the bandwidth of the system in byte per clock cycles (bandwidth = number of bytes per clock cycles) for the transfer of one block from Main Memory to Cache Memory for an interleaved main memory system with 23 banks (width of any bank: one word). Provide the solution with at least 2 decimals.
A given computer has a single cache memory (off-chip) with a 2 ns hit time and a 98% hitrate. Its main memory has 40 ns access time. What is the computer’s effective access time? If an on-chip cache with a 0.5 ns hit time and a 94% hit rate is added to it, what isthe computer’s new effective access time? How much of a speedup does the on-chip cache give the computer?
Suppose a specific MCU has the following size of memories: 2 M byte of flash, starting from 0x0800_0000, 256 k byte of SRAM starting from 0x2000_0000, and 8 k byte registers for GPIOs, start at 0x4001_0000. (Note that 0x is the prefix for hexadecimal numbers.) Draw the memory map based on your calculations for the addresses.
Suppose that a 2M × 16 main memory is built using 256K × 8 RAM chips and that memory is word addressable.1. a) How many RAM chips are necessary?2. b) If we were accessing one full word, how many chips would be involved? 3. c) How many address bits are needed for each RAM chip?4. d) How many banks will this memory have?5. e) How many address bits are needed for all memory?6. f) If high-order interleaving is used, where would address 14 (which is E in hex) be located?7. g) Repeat exercise 9f for low-order interleaving.
Suppose that a 4M × 32 main memory is built using 128K × 8 RAM chips and memory is word addressable (word size = 32 bits)a. How many RAM chips are needed?b. How many chips would be involved when accessing a full word?c. How many banks will this memory have?d. How many address bits are needed for the whole main memory?e. If high-order interleaving is used, where would the address 7060016 be located (in which bank)?f. If low-order interleaving is used, where would the address 2C77D516 be located?
Consider a cache memory with blocks of 23 = words (1 word = 4 bytes) , with a bus Main Memory - Cache of 32 bits, and with 1 clock cycle to send the address, a row cycle time (DRAM) of 17 cycles (5 less clock cycles for the column access time) and 1 clock cycle to return a word. Assuming that each word is in a different DRAM row, calculate the bandwidth of the system in byte per clock cycles (bandwidth = number of bytes per clock cycles) for the transfer of one block from Main Memory to Cache Memory (not interleaved memory system). Provide the solution with at least 2 decimals
A computer employs RAM chips of 512 x 4 and ROM chips of 256 x 8. The computer system needs 1KB of RAM, and 512 x 8 ROM and an interface unit with 256 registers each. A memory-mapped I/O configuration is used. The two higher -order bits of the address bus are assigned 00 for RAM, O1 for ROM, and 10 for interface. a) How many lines must be decoded for chip select? Specify the size of the decoder b) Draw a memory-address map for the system and Give the address range in hexadecimal for RAM, ROM c) Develop a chip layout for the above said specifications.
Suppose that a 64M x 16 main memory is built using 512K × 8 RAM chips and memory is word-addressable. a) How many RAM chips are necessary?b) If we were accessing one full word, how many chips would be involved?c) How many address bits are needed for each RAM chip?d) How many banks will this memory have?e) How many address bits are needed for all of memory?f) If high-order interleaving is used, where would address 32(base 10) be located? (Your answer should be "Bank#, Offset#")g) Repeat (f) for low-order interleaving.
Consider a memory system with the following parameters: Tc = 100ns Cc = 0.01 cents/bit Tm = 1,200ns Cm = 0.001 cents/bit a. What is the cost of 1 MByte of main memory? b. What is the cost of 1 MByte of main memory using cache memory technology?
Suppose that a 32M X 32 memory built using 512K X 8 RAM chips and memory is word-addressable. 1) How many RAM chips are necessary? 2) If we were accessing one full word, how many chips would be involved? 3) How many address bits are needed for each RAM chip? 4) How many banks will this memory have? 5f) If high-order interleaving is used, where would address 0x11011 be located? (Answer should be: bank# & offset#)
A 32-bit computer has a memory of 256 KB and a cache line size of 64 bytes. The memory cache access time is 5ns. This cache is 4-way associative and use LRU as a replacement algorithm. a) What is the number of lines and sets of this memory cache? b) What is the block size transferred between the cache memory and the main memory? c) If the time to transfer a line to cache memory is 200 ns, what is the hit ratio needed to obtain an average access time of 20 ns?