Given an instruction sequence with instructions in classes A, B, and C as the table below (same as the last two questions): Instruction Class A BC |CPI Instruction Count|10|40|10 2 1 3 Suppose we are considering improving the execution with the following restrictions: We can only select one class of instructions to improve; and • We will be able to reduce the execution time for the selected instruction class by 50%; No changes to other instructions. Which instruction class should we select to achieve the most improvement? class A class B class C Either one: the improvement will always be the same.

Given an instruction sequence with instructions in classes A, B, and C as the table below (same as the last two questions): Instruction Class A BC |CPI Instruction Count|10|40|10 2 1 3 Suppose we are considering improving the execution with the following restrictions: We can only select one class of instructions to improve; and • We will be able to reduce the execution time for the selected instruction class by 50%; No changes to other instructions. Which instruction class should we select to achieve the most improvement? class A class B class C Either one: the improvement will always be the same.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Consider a machine with three instruction classes and CPI measurements as follows: Instruction class CPI of the instruction class A 2 B 5 C 7 Suppose that we measured the code for a given program in two different compilers and obtained the following data: Code sequence Instruction counts (in millions) A B C 1 15 5 3 2 25 2 2 Assume that the machine’s clock rate is 500 MHz. Which code sequence will execute faster according to MIPS? How much according to execution time of each code sequence?
Suppose the implementation of an instruction set architecture uses three classes of instructions, which are called A, B, and C. The total dynamic instruction count is 1 x 10^7 and the processor's clock rate is 2.5 GHz. Details for the three classes are given in the table below: Class CPI % of instructions A 1 20% 50% C 3 30% Complete the following table. Express all answers in scientific notation and round to two decimal places, when needed. Class Instruction Count Number of Clock Cycles х 10^ x 10^ A х 10^ х 10^ x 10^ х 10^ C
Consider a multilevel computer in which levels are vertically stacked, with the lowest level being level 1. Each level has instructions that are m times as powerful as those of the level below it; that is, one level r instruction can do the work of m instructions at level r-1. However, n instructions at level r-1 are required to interpret each instruction at level r. Given this, answer the following questions: If a level 1 program requires k seconds to run, how long would the equivalent program take to run at levels 2, 3 and 4. Express your answer in terms of n, m, and r. What is the performance implication for the program if n > m? Conversely, what is the implication if m > n? Which case do you think more likely? Why?
Please,Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?.
Two algorithms A and B report time complexities expressed by the functions n2and 2n , respectively. They are to be executed on a machine M that consumes 10–6 s to execute an instruction. What is the time taken by the algorithms to complete their execution on machine A for an input size of 50? If another machine N that is 10 times faster than machine M is provided for the execution, what is the largest input size that can be handled by the two algorithms on machine N? What are yourobservations?
Consider two different implementations, M1 and M2, of the same instruction set. There arethree classes of instructions (A, B, and C) in the instruction set. M1 has a clock rate of 2.0GHz and M2has a clock rate of 2.5GHz. The average number of cycles for each instruction class and their frequencies(for a typical program) are as follows:Instruction Class M1-Cycles/InstructionClass M2 -Cycles/InstructionClasss FrequencyA 1 2 60%B 3 2 30%C 4 3 10%(a) Calculate the average CPI for each machine, M1, and M2.(b) Calculate the average MIPS ratings for each machine, M1 and M2.(c) Which machine has a smaller MIPS rating? Which individual instruction class CPI do you needto change, and by how much, to have this machine have the same or better performance as themachine with the higher MIPS rating (you can only change the CPI for one of the instructionclasses on the slower machine)?
10.- Consider the following code and pictureLoop1MOVLW 0x32MOVWF REG2DECFSZ REG2,FGOTO LOOP1 If the system clock frequency is aMHz and each machine cycle consumes 4 cycles of it. Calculate the delay time of the LOOP1 loop. Include the execution difference time of the DECFSZ instruction in the last cycle. Select an answerA) 0.6.sB) 6msC)6usD) 60us
Consider two different implementations, P1 and P2, of the same instruction setarchitecture. There are four classes of instructions (A, B, C, and D).P1 has a clock rate of 1.5 GHz and CPI for each instruction class is as follows:Class CPI for this classA 1B 2C 3D 4P2 has a clock rate of 2.0 GHz and CPI for each instruction class is as follows:Class CPI for this classA 2B 2C 2D 2a. Given a program with 106 instructions divided into classes as follows: 10% classA, 20% class B, 50% class C and 20% class D, which implementation is faster?
Calculate the CPU execution time (expressed in milliseconds) of a program with 10 million instructions on a 2.5 GHz CPU with the following basic instruction-type breakdowns and CPIs: Arithmetic: 60%, CPI = 2 Load & Store (assuming perfect caches): 25%, CPI = 5 Branching: 15%, CPI = 3 In addition, you are told that the overall cache miss rate for instructions is 1%, the overall cache miss rate for data is 3%, and the cache miss penalty is 100 cycles. You can ignore the hit time (consider it zero).
Consider a generic processor executing the following set of machine instructions. Memory location 34 contains a value 20. What statement best express the final outcome? MOV R1, #0 MOV R2, #34 MOV R3, #1034 ADD R1, (R2) MOV (R3), R1 Select one or more A. memory location 20 contains value 1034 B.memory location 1034 contains value 54 C. memory location 1034 contains value 34 D. memory location 20 contains value 34 E. memory location 1034 contains value 20
Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz.Computer B has a CPI of 2.5 and can be run at a clock rate of 750 Mhz. Wehave a particular program we wish to run. When compiled for computer A, thisprogram has exactly 100,000 instructions. How many instructions would theprogram need to have when compiled for Computer B, in order for the twocomputers to have exactly the same execution time for this program?
A particular (fictional) CPU has the following internal units and timings (WRand RR are write/read registers,ALU does all logic and integer operations and there is a separate floatingpoint unit FPU. Timings for each unit in picoseconds are:IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380(assume instruction read and memory access are average time for access tocache)There are 5 basic instruction types: - here are instruction sequence for eachtype, time in picoseconds and percentage of each type in a typical set of testcodes:1. LOAD : IR+RR+ALU+MEM+WR : 780, 20%2. STORE: IR+RR+ALU+MEM : 730, 10%3. LOGIC/INTEGER: IR+RR+ALU+WR : 520, 40%4. FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. BRANCH: IR+RR+ALU : 270, 20%1 cycle is 780ps = .780 nanoseconds for this machine, on the assumption thatall instructions take 1 cycle (assume all memory access is in cache). Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1