If CS=2000 H, DS=4000 H, SS=6000 H, ES=9000 H, BX=1358 H, BP=2122 H, SP=3500 H, SI=4100 H, DI=5147 H, IP=1547 H; Mention the addressing mode and calculate the 20 bit physical address of the instruction: MOV [BX+SI+1597H], AH
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A: Given:
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- In an architecture with 18 bits of "virtual address" width, "page size" is given as 1024 bytes and "physical address" width is given as 15 bits. TLB has a “2-way set associative” structure and contains a total of 16 data blocks. What is the TLB Tag field width in this architecture? A) 4 B) 5 C) 6 D) 7 E) 8Mapping from high level addresses to low level addresses is known as address resolution. True or False?c. Given a standard memory size of 215block, briefly explain how many addressable locations can beaccessed by an SIC machine and why
- Consider a system with 36-bit addresses that employs both segmentation and paging. Assume each PTE and STE is 4-bytes in size Assume the largest possible segment table is 213 bytes and the largest possible page table is 216 bytes. How large is a page? How large in bytes is the largest possible segment? please explain and don't paste the quizlet pictureSuppose a computer system uses 16-bit addresses for both its virtual and physical addresses. In addition, assume each page (and frame) has size 256 bytes. 8 bits are used for offset, 8 bits are used for page # and the max number of pages a process can have is 256. e. Translate the following virtual addresses to physical addresses, and show how you obtain the answers. (Hint: You do not need to convert hexadecimal numbers to decimal ones.) 0x0389 0xDF78 0x0245 0x8012 f) Now, suppose that the OS uses a two-level page table. Draw the page table. (Assume that frames 7 through 221 are free, so you can allocate space for the page table there.) In addition, suppose that the page-table directory storage comprises a whole number of consecutive full frames. (For examples: if the directory entry is 2 bytes, the entry’s storage comprises 1 frame; if the directory entry is 260 bytes, the entry’s storage comprises 2 consecutive frames.) g)What is the size of the two-level page table…For each of the following decimal virtual address : 32768, 60000. Compute the virtual page number and offset for 8KB page.
- Devise an addressing mechanism that allows an arbitrary set of 64 addresses, not necessarily contiguous, in a large address space to be specifiable in a 6-bit field.Consider the following segment table (all expressed and addressed in bytes) Segment Base Length 0 500 1000 1 4500 1500 2 7000 3000 3 11000 2400 4 15000 875 What are the physical addresses for the following logical addresses? a. 0,430 b. 1,1520 c. 2,500 d. 3,400 e. 4,1120For a microprocessor the code segment starts at 20000H, and stack segment starts at 21000H.Physical addresses from 21000H to 2FFFFH are accessible from both code and stack segment.These are the physical addresses.● If a location has CS: IP=2000H: 3000H, can we access this location with SS: SP? If yes,what is the SS: SP for this location? If no, why is it not accessible?● If another location has CS: IP=2000H: 0030H, can we access this location with SS: SP? Ifyes, what is the SS: SP for this location? If no, why is it not accessible?
- Answer the given question with a proper explanation and step-by-step solution. DON'T COPY PAST (f-bit) Suppose the size of logical address space is 2^1.MB, physical memory size is 2^8 MB, and page/frame size is 2^6 KB? How many bits will be used for frame number (what is f)? (Note: 2^a means 2 to the power a).Suppose the virtual address width is 32 bits. Also suppose that the virtual and physical page size is 4Kbytes. If the physical address limit is 220, what is the number of bits in the Physical frame part of the physical address?Consider a computer which uses virtual addressing with 32 bit addresses and a two level page table. The virtual addresses are split into a 9 bit top level page table field, an 11 bit second level page table field and an offset. How large are the pages and, how many are there in the address space?