2- Find the physical destination address of last instruction below MOV BX,0AAH MOV AX,1BBH MOV DS,AX MOV [BX],AX a) 1000H b) 10000H c) ОААН d) 1C5АН e) 01BBH f) 2F28H Boş bırak
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![2- Find the physical destination address of last instruction below.
MOV BX,0AAH
MOV AX,1BBH
MOV DS,AX
MOV [BX],AX
a)
1000H
b)
10000H
c) O OAAH
d)
1C5AH
e)
01BBH
f)
2F28H
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- I- Explain utiat haprns PUSH Bx instruction executes. Make sure to show where BH and BL are stored (assume that SP=OI OOh and SS=0200h) 2- Show the ending auress of each memory segments for the follow.ng segment register values: SS=ABCDw CS=EOOOh, DS=FOFOW cs=1234h 3- Sumx»se ECx-12345678h , EBx—876S4321h DS-1100tL Determine the contents of each address accessed by the following instructions: (a) MOV [EBx].ECx (b) MOV WORD PTRIEBx J, 1234bConsider the following store instruction: SW R1, 0x000F(R0). Assume that the registers R0 and R1 are initialized with 0x00000001 and 0x53A78BC Frespectively. A section of the MIPS byte addressable data memory is shown. Give the memory word of the following memory locations after the SW operation: (a). 0x00000015. (b). 0x00000014. (c). 0x00000013. (d) 0x00000012.(e). 0x00000011. (f). 0x00000010.a) Compute the binary representation of the following mips instruction: lw $t4, 5($s4) b) Compute the binary representation of the following mips instruction: ???? $?3, $?3, 7 C) Compute the binary representation of the following mips instruction: ?? $?2, 4($?3)
- Tutorial6 Questions on 8085 1. Find the machine codes of following 8085 instructions and in each case identify the opcodepart, and register/ memory reference bits. Also mention the length of opcode, number of bytesin the instruction.MOV A, M;MVI C, data;PUSH B;ADC B;XRA L;JNZ addressLDAX B 2. Translate the following Assembly program of 8085 into machine code (hex format) MVI C, 20LXI H, 1500hMVI A, 00next; MOV B, MADC BINX HDCR CJNZ nextSTA 1600hHLT Assume that the program is to be stored in memory starting at address 1000h 3. Find out the number of machine cycles and the number of T-states taken by the following8085 instructions. In each case give an explanation for your answer.(i) ADC D(ii) ADI 05(iii) JMP 1500h(iv) JNZ 1500h(v) LDAX B(vi) MOV A, B(vii) LDA 1300h 4. Draw a complete connection diagram of a computer system with 8085 as processor, a four 1KRAM, and four 1K ROM chips. Give the address range for each RAM and ROM chips.5. Translate the sumArray function (written in C…333: E8B3 8B3: 0A12 A12: 2153 Since the contents of the relevant addresses are 333 in the basic computer given above, the initial value of the PC is 333; When fetching and executing an indirectly addressing ISZ instruction, write the contents of the following registers in hexadecimal (hex) format for the T5 time. AR ........... DR......... IR ........... PC ........... SC ...........17. Consider the following hypothetical instruction: SubMem R1, mem1, mem2 This instruction works as follows: \[ \mathrm{R} 1 \leftarrow \text { [mem1] - [mem2] } \] In a multi-cycle datapath implementation, this instruction will: a. Use the MDR twice b. Use the ALU once c. Use the "shift to left" unit twice d. None of the above Answer: B 18. Consider the following hypothetical instruction: Mems mem1, R1, mem2 This instruction works as follows: \[ \text { [mem1] } \leftarrow \mathrm{R} 1 \text { - [mem2] } \] One of the following is correct about this instruction: a. It will not need theBregister b. It will require priting into MDR twice c. It will require writing into the ALUout three times d. None of the above Answer: A 19. By comparing the hypothetical instructions given in Questions (17) and (18), if we run these instructions on the same processor, then one of the following is correct: a. Both instructions have the same CPI b. Mems executes faster than SubMem c. SubMem executes…
- Consider the following instruction sequence where registers R1,R2 and R3 are general purpose and MEMORY[X] denotes the content at the memory location X. InstructionMOV R1,(5000)MOV R2,(R3)ADDR2,R1MOV (R3),R2INC R3DEC R1BNZ 1004HALTSemanticsR1←MEMORY[5000]R2←MEMORY[R3]R2←R1+R2MEMORY[R3]←R2R3←R3+1R1←R1−1Branch if not zero to thegiven absolute addressStopInstruction Size (bytes)44242221 Assume that the content of the memory location 5000 is 10, and the content of the register R3 is 3000. The content of each of the memory locations from 3000 to 3020 is 50. The instruction sequence starts from the memory location 1000. All the numbers are in decimal format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location 3010 ishelp for the mips code. Q1)Suppose $t1 stores the base address of word array A and $s2 is associated with h, convert to the following instruction into MIPS. if A[m+3]<20: A[m+1] = 5 else: A[m] = 1 Q2) Assume only $s1, $s2, $a0, $v0 registers can be used. Procedure calling convention MUST be followed. def func(x): a = x/3 if a == 20: return a else: return 1Question 26 Assume that EBX and ECX have the following values EBX: FF FF FF 75 ECX: 00 00 01 A2 After the execution of the instruction SUB EBX, ECX The Value in EBX is _________ Group of answer choices 000001A2 00000000 FFFFFDD3 none of them Question 27 Assume that EBX and ECX have the following values EBX: FF FF FF 75 ECX: 00 00 01 A2 After the execution of the instruction MOV EBX, ECX The Value in ECX is _________ Group of answer choices 000001A2 FFFFFF75 00000000 none of them
- 2- Show how each of the following MIPS instructions is converted into machine code. Assume the memory address of the first instruction is 100 hex. addi $t0, $Zero, -50 andi $t1, $t0, 7 Loop:and $t1,$t0,$t1 Sw $t0, 40 ($t1) Bne $t1,$ zero, LoopAssume the usage of ARM assembly language instruction: STR R0,[R1],#0x8. Assume that Register R0 contains 0xA0, Register R1 contains 0x7008. Identify (i) contents of memory location 0x00A8 and (ii) R1 after executing the given instruction (i) 0xA0, (ii) 0x7008 (i) 0xA0, (ii) 0x7011 (i) 0xA2, (ii) 0x7008 (i) 0xA2, (ii) 0x70101. T/F - if (B)=006000 (PC)=003600 (X)=000090, for the machine instruction 0x032026, the target address is 003000.2. T/F – PC register stores the return address for subroutine jump.3. T/F – S register contains a variety of information such as condition code.4. T/F – INPUT WORD 1034 – This means Operating system should reserve 1034 bytes in memory5. T/F - In a two pass assembler, adding literals to literal table and address resolution of local symbol are done using first pass and second pass respectively.