Q.2 Refer to Figure Q.2. (a) Determine the operation performed in this circuit at output of Reg A and Reg B according to input GT by completing Table Q.2(a) in the appendix page 14. (b) Modify the circuit in Figure Q.2 to consider input EQ as shown in Table Q.2(b) with minimum number of logic components. Draw the new circuit. X is don't care. EQ 0 GT 1 Mux Mua 2 GT 0 1 Figure Q.2 Table Q.2(a) Reg A Table Q.2(b) GT 0 Adder 1 X Mux Reg B Reg A CLK hold Reg A Reg B Reg B As your answer in Table Q.2(a) hold
Q.2 Refer to Figure Q.2. (a) Determine the operation performed in this circuit at output of Reg A and Reg B according to input GT by completing Table Q.2(a) in the appendix page 14. (b) Modify the circuit in Figure Q.2 to consider input EQ as shown in Table Q.2(b) with minimum number of logic components. Draw the new circuit. X is don't care. EQ 0 GT 1 Mux Mua 2 GT 0 1 Figure Q.2 Table Q.2(a) Reg A Table Q.2(b) GT 0 Adder 1 X Mux Reg B Reg A CLK hold Reg A Reg B Reg B As your answer in Table Q.2(a) hold
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
Related questions
Question
![Q.2 Refer to Figure Q.2.
(a) Determine the operation performed in this circuit at output of Reg A and Reg B
according to input GT by completing Table Q.2(a) in the appendix page 14.
(b) Modify the circuit in Figure Q.2 to consider input EQ as shown in Table Q.2(b) with
minimum number of logic components. Draw the new circuit. X is don't care.
EQ
0
GT
1
Max 2
Mus Z
GT
0
1
Figure Q.2
Table Q.2(a)
Reg A
Adder
Table Q.2(b)
GT
0
1
X
Mux Z
Reg B
Reg A
CLK
hold
Reg A
Reg B
Reg B
As your answer
in Table Q.2(a)
hold](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F362f3815-bb27-44c8-8809-76a45a2e0d62%2F81de6430-3bd1-4f4f-b4a8-38cd8dd5e830%2Fajsjyes_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Q.2 Refer to Figure Q.2.
(a) Determine the operation performed in this circuit at output of Reg A and Reg B
according to input GT by completing Table Q.2(a) in the appendix page 14.
(b) Modify the circuit in Figure Q.2 to consider input EQ as shown in Table Q.2(b) with
minimum number of logic components. Draw the new circuit. X is don't care.
EQ
0
GT
1
Max 2
Mus Z
GT
0
1
Figure Q.2
Table Q.2(a)
Reg A
Adder
Table Q.2(b)
GT
0
1
X
Mux Z
Reg B
Reg A
CLK
hold
Reg A
Reg B
Reg B
As your answer
in Table Q.2(a)
hold
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